16F876 データシートの表示（PDF） - Microchip Technology

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16F876

28/40/44-Pin Enhanced Flash Microcontrollers

Microchip Technology 

PIC16F87X

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Details

on

page:

Bank 2

100h(3) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000

101h

102h(3)

103h(3)

104h(3)

TMR0

PCL

STATUS

FSR

Timer0 Module Register

Program Counter’s (PC) Least Significant Byte

IRP

RP1

RP0

TO

PD

Indirect Data Memory Address Pointer

xxxx xxxx

0000 0000

Z

DC

C

0001 1xxx

xxxx xxxx

105h

—

Unimplemented

—

106h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

107h

—

Unimplemented

—

108h

—

Unimplemented

—

109h

10Ah(1,3)

10Bh(3)

—

PCLATH

INTCON

Unimplemented

—

—

GIE

PEIE

—

T0IE

Write Buffer for the upper 5 bits of the Program Counter

INTE

RBIE

T0IF

INTF

RBIF

—

---0 0000

0000 000x

10Ch

EEDATA

EEPROM Data Register Low Byte

xxxx xxxx

10Dh

EEADR

EEPROM Address Register Low Byte

xxxx xxxx

10Eh

EEDATH

—

—

EEPROM Data Register High Byte

xxxx xxxx

10Fh

EEADRH

—

—

—

EEPROM Address Register High Byte

xxxx xxxx

Bank 3

180h(3) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000

181h

OPTION_REG RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0 1111 1111

182h(3) PCL

Program Counter (PC) Least Significant Byte

0000 0000

183h(3) STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx

184h(3) FSR

Indirect Data Memory Address Pointer

xxxx xxxx

185h

—

Unimplemented

—

186h

TRISB

PORTB Data Direction Register

1111 1111

187h

—

Unimplemented

—

188h

—

Unimplemented

—

189h

18Ah(1,3)

18Bh(3)

—

PCLATH

INTCON

Unimplemented

—

—

GIE

PEIE

—

T0IE

Write Buffer for the upper 5 bits of the Program Counter

INTE

RBIE

T0IF

INTF

RBIF

—

---0 0000

0000 000x

18Ch

EECON1

EEPGD

—

—

—

WRERR WREN

WR

RD x--- x000

18Dh

EECON2

EEPROM Control Register2 (not a physical register)

---- ----

18Eh

—

Reserved maintain clear

0000 0000

18Fh

—

Reserved maintain clear

0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.

3: These registers can be addressed from any bank.

4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.

5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.

27

47

26

18

27

—

31

—

—

—

26

20

41

41

41

41

27

19

26

18

27

—

31

—

—

—

26

20

41, 42

41

—

—

 2001 Microchip Technology Inc.

DS30292C-page 17

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