K9MCG08U5M-P データシートの表示（PDF） - Samsung
部品番号
コンポーネント説明
メーカー
K9MCG08U5M-P Datasheet PDF : 45 Pages
| |||
K9HBG08U1M
K9LAG08U0M K9MCG08U5M
Advance
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
K9LAG08U0M
K9HBG08U1M
K9MCG08U5M
NVB
7,992
-
8,192
Blocks
NVB
15,984
-
16,384
Blocks
NVB
31,968
-
32,768
Blocks
NOTE :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is
presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-
gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
* : Each K9LAG08U0M chip in the K9HBG08U1M and K9MCG08U5M has Maximun 200 invalid block.
AC TEST CONDITION
(K9XXG08UXM-XCB0:TA=0 to 70°C,K9XXG08UXM-XIB0:TA=-40 to 85°C, K9XXG08UXM: Vcc=2.7V~3.6V unless otherwise noted )
Parameter
K9XXG08UXM
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
1 TTL GATE and CL=50pF (K9LAG08U0M-Y,P/K9HBG08U1M-I)
Output Load (Vcc:3.0V +/-10%)
1 TTL GATE and CL=30pF (K9HBG08U1M-Y,P)
1 TTL GATE and CL=30pF (K9MCG08U5M-Y,P)
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test
Condition
Min
Input/Output Capacitance
CI/O
VIL=0V
-
Input Capacitance
CIN
VIN=0V
-
NOTE : Capacitance is periodically sampled and not 100% tested.
K9HBG08U1M-IXBO’s capacitance(I/O, Input) is 20pF.
K9LAG08U0M
20
20
Max
K9HBG08U1M
40
40
Unit
K9MCG08U5M
80
pF
80
pF
MODE SELECTION
CLE
ALE
CE
WE
RE
H
L
L
H
L
H
L
H
H
L
L
H
L
H
L
H
L
L
L
H
L
L
L
H
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X(1)
X
X
X
X
X
H
X
X
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
WP
X
X
H
H
H
X
X
H
H
L
0V/VCC(2)
Mode
Read Mode
Command Input
Address Input(5clock)
Write Mode
Command Input
Address Input(5clock)
Data Input
Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
13
Share Link: 