GM2125 データシートの表示（PDF） - Genesis Microchip

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GM2125

Analog Interface XGA/SXGA OnPanel LCD Panel Controller

Genesis Microchip 

*** Genesis Microchip Confidential ***

gm2115/25 Preliminary Data Sheet

5. Half Reference Clock (RCLK/2) is the RCLK (see 2, above) divided by 2. Used as

OCM_CLK domain driver.

6. Quarter Reference Clock (RCLK/4) is the RCLK (see 2, above) divided by 4. Used as

alternative clock (faster than TCLK) to drive IFM.

8. ADC Output Clock (SENSE_ACLK) is a delay-adjusted ADC sampling clock, ACLK.

ACLK is derived from SCLK.

HSYNC

SDDS

SCLK

TCLK

RCLK

PLL

IP_CLK

DDDS

DCLK

/2

RCLK/2

/4

RCLK/4

Figure 8.

Internally Synthesized Clocks

The on-chip clock domains are selected from the synthesized clocks as shown in Figure 9

below. These include:

1. Input Domain Clock (IP_CLK). Max = 165MHz

2. Host Interface and On-Chip Microcontroller Clock (OCM_CLK). Max = 100MHz

3. Filter and Display Pixel Clock (DP_CLK). Max = 135MHz

4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz

5. ADC Domain Clock (ACLK). Max = 165MHz.

The clock selection for each domain as shown in the figure below is controlled using the

CLOCK_CONFIG registers (index 0x03 and 0x04).

June 2002

19

C2115-DAT-01B

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