5962F9563501QXC データシートの表示（PDF） - Intersil
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5962F9563501QXC Datasheet PDF : 36 Pages
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TCLK
RISING
EDGE
TOP
REGISTER
HS-RTX2010RH
TCLK
RISING
EDGE
INTA CYCLE OR
ASIC READ COMMAND
PRELOAD
REGISTER
TP0
LOAD TC0
TIMER/COUNTER
PRELOAD
REGISTER
TP1
LOAD TC1
TIMER/COUNTER
PRELOAD
REGISTER
TP2
LOAD TC2
TIMER/COUNTER
EXECUTE
COUNT
ACTIVATE
TIMEOUT
INTERRUPT
EXECUTE
COUNT
ACTIVATE
TIMEOUT
INTERRUPT
EXECUTE
COUNT
ACTIVATE
TIMEOUT
INTERRUPT
INTERRUPT
CONTROLLER
INTERRUPT
RESET
INTERRUPT
RESET
INTERRUPT
RESET
FIGURE 23. HS-RTX2010RH TIMER/COUNTER OPERATION
TABLE 3. TIMER/COUNTER
IBC BIT VALUES
TIMER CLOCK SOURCE
BIT 09
BIT 08
TC2
TC1
0
0
TCLK
TCLK
0
1
TCLK
TCLK
1
0
TCLK
EI4
1
1
EI5
EI4
TC0
TCLK
EI3
EI3
EI3
HS-RTX2010RH Interrupt Controller
The HS-RTX2010RH Interrupt Controller manages interrupts
for the HS-RTX2010RH Microcontroller core. Its sources
include two on-chip peripherals and six external interrupt
inputs. The two classes of on-chip peripherals that produce
interrupts are the Stack Controllers and the Timer/Counters.
Interrupt Controller Operation
When one of the interrupt sources requests an interrupt, the
Interrupt Controller checks whether the interrupt is masked
in the Interrupt Mask Register. If it is not, the controller
attempts to interrupt the processor. If processor interrupts
are enabled (bit 4 of the Configuration Register), the
processor will execute an Interrupt Acknowledge cycle,
during which it disables interrupts to ensure proper
completion of the INTA cycle.
In response to the Interrupt Acknowledge cycle, the Interrupt
Controller places an Interrupt Vector on the internal ASIC
Bus, based on the highest priority pending interrupt. The
processor performs a special Subroutine Call to the address
in Memory Page 0 contained in the vector. This special
subroutine call is different in that it saves a status bit on the
Return Stack indicating the call was caused by an interrupt.
Thus, when the Interrupt Handler executes a Subroutine
Return, the processor knows to automatically re-enable
interrupts. Before the Interrupt Handler returns, it must
ensure that the condition that caused the interrupt is cleared.
Otherwise the processor will again be interrupted
immediately upon its return.
Processor interrupts are enabled and disabled by clearing
and setting the Interrupt Disable Flag. When the RTX is
reset, this flag is set (bit 04 of the CR = 1), disabling the
interrupts. This bit is a write-only bit that always reads as 0,
allowing interrupts to be enabled in only 2 cycles with a
simple read/write operation in which the processor reads the
bit value, then writes it back to the same location. The actual
status of the Interrupt Disable Flag can be read from bit 14
of CR .
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