ADP3110A データシートの表示（PDF） - Analog Devices

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ADP3110A

Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

Analog Devices 

ADP3110A

The MOSFET vendor should provide a rating for the maximum

voltage slew rate at drain current around which this can be

designed. When this rating is obtained, determine the expected

maximum current in the MOSFET by

I MAX

= I DC ( per

phase) + (VCC

−VOUT )×

DMAX

f MAX × LOUT

(7)

where:

DMAX is determined for the VR controller that is used with the

driver. This current is divided roughly equally between

MOSFETs if more than one is used (assume a worst-case

mismatch of 30% for design margin).

LOUT is the output inductor value.

When producing the design, there is no exact method for

calculating the dV/dt due to the parasitic effects in the external

MOSFETs as well as the PCB. However, it can be measured to

determine if it is safe. If it appears the dV/dt is too fast, an

optional gate resistor can be added between DRVH and the

high-side MOSFETs. This resistor slows down the dV/dt, but it

also increases the switching losses in the high-side MOSFETs.

The ADP3110A is optimally designed with an internal drive

impedance that works with most MOSFETs to switch them

efficiently, yet minimizes dV/dt. However, some high speed

MOSFETs can require this external gate resistor, depending on

the currents being switched in the MOSFET.

Low-Side (Synchronous) MOSFETs

The low-side MOSFETs are usually selected to have a low on

resistance to minimize conduction losses. This usually implies a

large input gate capacitance and gate charge. The first concern is

to ensure the power delivery from the ADP3110A DRVL does

not exceed the thermal rating of the driver (see the ADP3186,

ADP3188, or ADP3189 data sheets for Flex-Mode controller

details).

The next concern for the low-side MOSFETs is to prevent them

from inadvertently being switched on when the high-side

MOSFET turns on. This occurs due to the drain gate (Miller

capacitance, also specified as Crss capacitance) of the MOSFET.

When the drain of the low-side MOSFET is switched to VCC by

the high-side turning on (at a rate dV/dt), the internal gate of

the low-side MOSFET is pulled up by an amount roughly equal

to VCC × (Crss/Ciss). It is important to make sure this does not put

the MOSFET into conduction.

Another consideration is the nonoverlap circuitry of the

ADP3110A that attempts to minimize the nonoverlap period.

During the state of the high-side turning off to low-side turning

on, the SW pin and the conditions of SW prior to switching are

monitored to adequately prevent overlap.

However, during the low-side turn-off to high-side turn-on, the

SW pin does not contain information for determining the

proper switching time, so the state of the DRVL pin is monitored

to go below one sixth of VCC; then, a delay is added. Due to the

Miller capacitance and internal delays of the low-side MOSFET

gate, ensure the Miller-to-input capacitance ratio is low enough,

and the low-side MOSFET internal delays are not so large as to

allow accidental turn on of the low-side MOSFET when the

high-side MOSFET turns on.

Contact Sales for an updated list of recommended low-side

MOSFETs.

PC BOARD LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed

circuit boards:

• Trace out the high current paths and use short, wide

(>20 mil) traces to make these connections.

• Minimize trace inductance between the DRVH and DRVL

outputs and the MOSFET gates.

• Connect the PGND pin of the ADP3110A as closely as

possible to the source of the lower MOSFET.

• Locate the VCC bypass capacitor as closely as possible to the

VCC and PGND pins.

• Use vias to other layers, when possible, to maximize

thermal conduction away from the IC.

The circuit in Figure 15 shows how four drivers can be

combined with the ADP3181 to form a total power conversion

solution for generating VCC(CORE) for an Intel® CPU that is

VRD 10.x compliant.

Figure 14 shows an example of the typical land patterns based

on the guidelines given previously. For more detailed layout

guidelines for a complete CPU voltage regulator subsystem,

refer to the Layout and Component Placement section in the

ADP3181 data sheet.

CBST1

CBST2

RBST

D1

CVCC

Figure 14. External Component Placement Example

Rev. 0 | Page 11 of 16

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