ADP3208CJCPZ-RL データシートの表示（PDF） - ON Semiconductor
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ADP3208CJCPZ-RL
ON Semiconductor
ADP3208CJCPZ-RL Datasheet PDF : 41 Pages
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ADP3208C
Pin No.
16
17
18
Mnemonic
LLINE
CSCOMP
CSREF
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 to 45
46
47
48
CSSUM
RAMP
ILIMN
ILIMP
RT
GND
BST2
DRVH2
SW2
PVCC2
DRVL2
PGND2
PGND1
DRVL1
PVCC1
SW1
DRVH1
BST1
VCC
SP
VID6 to VID0
PSI
DPRSTP
DPRSLP
Description
Load Line Programming Input. The center point of a resistor divider connected between CSREF and
CSCOMP can be tied to this pin to set the load line slope.
Current Sense Amplifier Output and Frequency Compensation Point.
Current Sense Reference Input. This pin must be connected to the common point of the output
inductors. The node is shorted to GND through an internal switch when the chip is disabled to
provide soft stop transient control of the converter output voltage.
Current Sense Summing Input. External resistors from each switch node to this pin sum the
inductor currents to provide total current information.
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this
pin sets the slope of the internal PWM stabilizing ramp used for phase-current balancing.
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current-limit threshold of the
converter.
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current-limit threshold of the
converter.
PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM
oscillator frequency.
Analog and Digital Signal Ground.
High-Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped
voltage while the high-side MOSFET is on.
High-Side Gate Drive Output for Phase 2.
Current Balance Input for Phase 2 and Current Return for High-Side Gate Drive.
Power Supply Input/Output of Low-Side Gate Driver for Phase 2.
Low-Side Gate Drive Output for Phase 2.
Low-Side Driver Power Ground for Phase 2.
Low-Side Driver Power Ground for Phase 1.
Low-Side Gate Drive Output for Phase 1.
Power Supply Input/Output of Low-Side Gate Driver for Phase 1.
Current Balance Input for Phase 1 and Current Return For High-Side Gate Drive.
High-Side Gate Drive Output for Phase 1.
High-Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped
voltage while the high-side MOSFET is on.
Power Supply Input/Output of the Controller.
Single-Phase Select Input. Logic high state sets single-phase configuration.
Voltage Identification DAC Inputs. A 7-bit word (the VID code) programs the DAC output voltage,
the reference voltage of the voltage error amplifier without a load (see the VID code table, Table 6).
Power State Indicator Input. Driving this pin low forces the controller to operate in single-phase mode.
Deeper Stop Control Input. The logic state of this pin is usually complementary to the state of the
DPRSLP pin; however, during slow deeper sleep exit, both pins are logic low.
Deeper Sleep Control Input.
Rev. 1 | Page 12 of 41 | www.onsemi.com
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