AV2722 データシートの表示（PDF） - Unspecified

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AV2722

AUDIO CODEC WITH HEADPHONE DRIVER AND PROGRAMMABLE SAMPLE RATES

Unspecified 

AV2722 (Preliminary)

I2S MODE

In I2S Mode, the MSB of the audio data SDI is sampled on the second rising edge of SC following SFDA/SFAD

transition. SFDA/SFAD are low during the left channel samples and high during the right channel samples.

SFDA (PIN 4) OR

SFAD (PIN 6)

Left channel

1/fs

Right channel

SC (PIN 2)

SDI (PIN 3)

(16-BIT AUDIO DATA)

15 14

MSB

210

LSB

15 14

MSB

210

LSB

SDI (PIN 3)

(18-BIT AUDIO DATA)

17 16

MSB

210

LSB

17 16

MSB

210

LSB

SDI (PIN 3)

(20-BIT AUDIO DATA)

19 18

MSB

21 0

LSB

19 18

MSB

21 0

LSB

SDI (PIN 3)

(24-BIT AUDIO DATA)

23 22 21

MSB

210

LSB

"I 2S" Data Input Timing

23 22 21

MSB

210

LSB

Normal Mode

In Normal Mode, the audio data, SDI, is right-justified. The LSB are aligned with the rising/falling edge of SFDA/

SFAD. Data is latched into the chip on the rising edge of SC. SFDA/SFAD are high during the left channel samples

and low during the right channel samples.

SFDA (PIN4) OR

SFAD (PIN 6)

SC (PIN 2)

SDI (PIN3) 2 1 0

(16-BIT AUDIO DATA)

SDI (PIN3) 2 1 0

(18-BIT AUDIO DATA)

SDI (PIN3) 2 1 0

(20-BIT AUDIO DATA)

SDI (PIN3) 2 1 0

(24-BIT AUDIO DATA)

Left channel

1/fs

Right channel

15 14

MSB

210

LSB

15 14

MSB

17 16

MSB

210

LSB

17 16

MSB

19 18

MSB

21 0

LSB

19 18

MSB

23 22 21

MSB

210

LSB

23 22 21

MSB

"Normal" Data Input Timing

210

LSB

210

LSB

2

1

0

LSB

210

LSB

8-29

January 22, 2004

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