CS61575 データシートの表示（PDF） - Cirrus Logic

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CS61575

T1/E1 Line Interface

Cirrus Logic 

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CS61574A CS61575

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Figure 13. Input/Output Timing

An address/command byte, shown in Table 9, pre-

cedes a data register. The first bit of the

address/command byte determines whether a read

or a write is requested. The next six bits contain

the address. The line interface responds to address

16 (0010000). The last bit is ignored.

,3"FIRSTBIT 













-3"LASTBIT 

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Table 9. Address/Command Byte

The data register, shown in Table 10, can be writ-

ten to the serial port. Data is input on the eight

clock cycles immediately following the ad-

dress/command byte. Bits 0 and 1 are used to

clear an interrupt issued from the INT pin, which

occurs in response to a loss of signal or a problem

with the output driver.

Writing a "1" to either "Clear LOS" or "Clear

DPM" over the serial interface has three effects:

1) The current interrupt on the serial interface

will be cleared. (Note that simply reading

the register bits will not clear the inter-

rupt).

2) Output data bits 5, 6 and 7 will be reset as

appropriate.

3) Future interrupts for the corresponding LOS

or DPM will be prevented from occurring.

Writing a "0" to either "Clear LOS" or "Clear

DPM" enables the corresponding interrupt for

LOS or DPM.

Output data from the serial interface is presented

as shown in Tables 11 and 12. Bits 2, 3 and 4 can

be read to verify line length selection. Bits 5, 6

and 7 must be decoded. Codes 101, 110 and 111

(Bits 5, 6 and 7) indicate intermittent loss of sig-

nal and/or driver problems.

SDO goes to a high impedance state when not in

use. SDO and SDI may be tied together in appli-

cations where the host processor has a

bi-directional I/O port.

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IN  CLR$0- #LEAR$RIVER0ERFORMANCE

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-3"LASTBIT  4!/3 4RANSMIT!LL/NES3ELECT

IN

Table 10. Input Data Register

18

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IN 







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Table 11. Output Data Bits 0 - 4

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