CY7C1011CV33-10BVI データシートの表示（PDF） - Cypress Semiconductor
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CY7C1011CV33-10BVI Datasheet PDF : 11 Pages
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CY7C1011CV33
AC Switching Characteristics Over the Operating Range[4] (continued)
Parameter
Write Cycle[8, 9]
Description
tWC
Write Cycle Time
tSCE
CE LOW to Write End
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[7]
WE LOW to High-Z[6, 7]
Byte Enable to End of Write
–10
–12
–15
Min. Max. Min. Max. Min. Max. Unit
10
12
15
ns
7
8
10
ns
7
8
10
ns
0
0
0
ns
0
0
0
ns
7
8
10
ns
5
6
7
ns
0
0
0
ns
3
3
3
ns
5
6
7
ns
7
8
10
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
VDR > 2V
3.0V
tCDR
tR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Notes:
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
11. WE is HIGH for read cycle.
Document #: 38-05232 Rev. *E
Page 5 of 11
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