CY7C1012AV33 データシートの表示（PDF） - Cypress Semiconductor

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CY7C1012AV33

512K x 24 Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Write Cycle No. 1 (CE Controlled)[2, 14, 15]

ADDRESS

CE

tSA

WE

DATA I/O

tWC

tSCE

tSCE

tAW

tPWE

tSD

DATA VALID

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]

tWC

ADDRESS

tSCE

CE

tAW

tSA

tPWE

WE

CY7C1012AV33

tHA

tHD

tHA

OE

DATA I/O

NOTE 16

tHZOE

Write Cycle No. 3 (WE Controlled, OE LOW)[2, 15]

tSD

DATAIN VALID

tWC

ADDRESS

CE

tSA

WE

tSCE

tAW

tPWE

tSD

DATA I/O

NOTE 16

DATA VALID

tHZWE

Notes:

14. Data I/O is high impedance if OE = VIH.

15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

16. During this period the I/Os are in the output state and input signals should not be applied.

Document #: 38-05254 Rev. *D

tHD

tHA

tHD

tLZWE

Page 6 of 9

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