CY3682(2004) データシートの表示（PDF） - Cypress Semiconductor
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CY3682 Datasheet PDF : 42 Pages
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FO R
FO R
CY7C68001
7.9.2 EPxEF Bit 5, Bit 1
This bit is the current state of endpoint x’s empty flag. EPxEF
= 1 if the endpoint is empty.
7.9.3 EPxFF Bit 4, Bit 0
This bit is the current state of endpoint x’s full flag. EPxFF = 1
if the endpoint is full.
7.10 INPKTEND/FLUSH Register 0x20
This register allows the external master to duplicate the
function of the PKTEND pin. The register also allows the
external master to selectively flush endpoint FIFO buffers.
INPKTEND/FLUSH
0x20
Bit #
7
6
5
4
3
2
1
0
Bit Name FIFO8 FIFO6 FIFO4 FIFO2 EP3 EP2 EP1 EP0
Read/Write W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
Bit [4..7]: FIFOx
These bits allows the external master to selectively flush any
or all of the endpoint FIFOs. By writing the desired endpoint
FIFO bit, SX2 logic flushes the selected FIFO. For example
setting bit 7 flushes endpoint 8 FIFO.
Bit [3..0]: EPx
These bits are is used only for IN transfers. By writing the
desired endpoint number (2,4,6 or 8), SX2 logic automatically
commits an IN buffer to the USB host. For example, for
committing a packet through endpoint 6, set the lower nibble
to 6: set bits 1 and 2 high.
7.11 USBFRAMEH/L Registers 0x2A, 0x2B
Every millisecond, the USB host sends an SOF token
indicating “Start Of Frame,” along with an 11-bit incrementing
frame count. The SX2 copies the frame count into these
registers at every SOF.
USBFRAMEH
0x2A
Bit #
7
6
5
4
3
2
1
0
Bit Name
0
0
0
0
0 FC10 FC9 FC8
Read/Write R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
x
USBFRAMEL
0x2B
Bit #
7
6
5
4
3
2
1
0
Bit Name FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0
Read/Write R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
One use of the frame count is to respond to the USB
SYNC_FRAME Request. If the SX2 detects a missing or
garbled SOF, the SX2 generates an internal SOF and incre-
ments USBFRAMEL–USBRAMEH.
7.12 MICROFRAME Registers 0x2C
MICROFRAME
0x2C
Bit #
7
6
5
4
3
2
1
0
Bit Name
0
0
0
0
0 MF2 MF1 MF0
Read/Write R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
x
MICROFRAME contains a count 0–7 that indicates which of
the 125 microsecond microframes last occurred.
This register is active only when SX2 is operating in high-
speed mode (480 Mbits/sec).
7.13 FNADDR Register 0x2D
During the USB enumeration process, the host sends a device
a unique 7-bit address that the SX2 copies into this register.
There is normally no reason for the external master to know
its USB device address because the SX2 automatically
responds only to its assigned address.
FNADDR
0x2D
Bit #
7
6
5
4
3
2
1
0
Bit Name HSGRANT FA6 FA5 FA4 FA3 FA2 FA1 FA0
Read/Write
R
RRRRRRR
Default
0
0
0
0
0
0
0
0
Bit 7: HSGRANT, Set to 1 if the SX2 enumerated at high
speed. Set to 0 if the SX2 enumerated at full speed.
Bit[6..0]: Address set by the host.
7.14 INTENABLE Register 0x2E
This register is used to enable/disable the various interrupt
sources, and by default all interrupts are enabled.
INTENABLE
0x2E
Bit #
7
6
5
43
2
1
0
Bit Name
SETUP EP0 FLAGS 1
BUF
1 ENUM BUS READY
OK ACTIVITY
Read/Write R/W R/W R/W R/W R/W R/W R/W
R/W
Default
1
1
1
11
1
1
1
7.14.1 SETUP Bit 7
Setting this bit to a 1 enables an interrupt when a set-up packet
is received from the USB host.
7.14.2 EP0BUF Bit 6
Setting this bit to a 1 enables an interrupt when the Endpoint
0 buffer becomes available.
7.14.3 FLAGS Bit 5
Setting this bit to a 1 enables an interrupt when an OUT
endpoint FIFO’s state transitions from empty to not-empty.
7.14.4 ENUMOK Bit 2
Setting this bit to a 1 enables an interrupt when SX2 enumer-
ation is complete.
7.14.5 BUSACTIVITY Bit 1
Setting this bit to a 1 enables an interrupt when the SX2
detects an absence or presence of bus activity.
Document #: 38-08013 Rev. *E
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