CY7C68001(2004) データシートの表示（PDF） - Cypress Semiconductor

部品番号

コンポーネント説明

メーカー

CY7C68001
(Rev.:2004)

High-Speed USB Interface Device

Cypress Semiconductor 

FO R

FO R

CY7C68001

11.5 Slave FIFO Output Enable

Following timings are applicable to synchronous and asynchronous interfaces.

SLOE

DATA

tOEon

tOEoff

Figure 11-14. Slave FIFO Output Enable Timing Diagram[11]

Table 11-19. Slave FIFO Output Enable Parameters

Parameter

tOEon

tOEoff

Description

SLOE assert to FIFO DATA Output

SLOE deassert to FIFO DATA Hold

Min.

Max.

10.5

10.5

Unit

ns

ns

11.6 Sequence Diagram

11.6.1 Single and Burst Synchronous Read Example

tIFCLK

IFCLK

FIFOADR

t=0

SLRD

SLCS

tSFA

tFAH

tSRD

tRDH

t=2

t=3

tSFA

T=0

>= tSRD

T=2

tFAH

>= tRDH

T=3

FLAGS

DATA

SLOE

tXFLG

tXFD

Data Driven: N

N+1

tOEon

tOEoff

tOEon

tXFD

N+1

tXFD

N+2

tXFD

N+3

N+4

tOEoff

t=1

t=4

T=1

T=4

Figure 11-15. Slave FIFO Synchronous Read Sequence and Timing Diagram

FIFO POINTER

IFCLK

N

SLOE

FIFO DATA BUS Not Driven

IFCLK

N

SLRD

Driven: N

IFCLK

N+1

N+1

SLOE

SLRD

IFCLK

N+1

IFCLK

N+1

IFCLK

N+2

SLOE

SLRD

Not Driven

N+1

N+2

IFCLK

N+3

N+3

IFCLK

N+4

SLRD

N+4

IFCLK

N+4

SLOE

N+4

IFCLK

N+4

Not Driven

Figure 11-16. Slave FIFO Synchronous Sequence of Events Diagram

Document #: 38-08013 Rev. *E

Page 31 of 42

Share Link: