FS6370-01G-XTD データシートの表示（PDF） - ON Semiconductor
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FS6370-01G-XTD Datasheet PDF : 28 Pages
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FS6370
Table 13: AC Timing Specifications
Parameter
Overall
EEPROM Write Cycle Time
Output Frequency *
VCO Frequency *
VCO Gain *
Loop Filter Time Constant *
Rise Time *
Fall Time *
Tristate Enable Delay *
Symbol Conditions/Description
Twc
fO
fVCO
AVCO
tr
tf
tPZL, tPZH
VDD = 5.5 V
VDD = 3.6 V
VDD = 5.5 V
VDD = 3.6 V
LFTC bit = 0
LFTC bit = 1
VO = 0.5 V to 4.5 V; CL = 15pF
VO = 0.3 V to 3.0 V; CL = 15pF
VO = 4.5 V to 0.5 V; CL = 15pF
VO = 3.0 V to 0.3 V; CL = 15pF
Clock
(MHz)
Tristate Disable Delay *
tPZL, tPZH
Clock Stabilization Time *
Output active from power-up, RUN mode via PD pin
tSTB
After last register is written, register program mode
Divider Modulus
Feedback Divider
NF
See also Error! Reference source not found.
Reference Divider
NR
Post Divider
NP
See also Error! Reference source not found.
Clock Output (PLL A clock via CLK_A pin)
Duty Cycle *
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak)
*
Tj(LT)
tj(ΔP)
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other
PLLs active
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, =14.318MHz, NF=220, NR=63, NPX=50, all other
PLLs active (B=60MHz, C=40MHz, D=14.318MHz)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs
active
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs
active (B=60MHz, C=40MHz, D=14.318MHz)
Clock Output (PLL B clock via CLK_B pin)
Duty Cycle *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak)
*
Tj(LT)
tj(ΔP)
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other
PLLs active
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, =14.318MHz, NF=220, NR=63, NPX=50, all other
PLLs active (A=50MHz, C=40MHz, D=14.318MHz)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs
active
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs
active (A=50MHz, C=40MHz, D=14.318MHz)
100
100
50
100
50
100
100
60
100
60
Min.
0.8
0.8
40
40
1
1
8
1
1
45
45
Typ.
400
7
20
2.0
2.1
1.8
1.9
100
45
165
110
390
45
75
120
400
Max. Units
4
ms
150
MHz
100
230
MHz
170
MHz/V
μs
ns
ns
8
ns
8
ns
μs
1
ms
2047
255
50
55
%
ps
ps
55
%
ps
ps
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