H27UAG8T2B データシートの表示（PDF） - Hynix Semiconductor
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H27UAG8T2B Datasheet PDF : 61 Pages
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Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
■ Figure 63. Restriction read status in multi plane operation
I/Ox
R/B#
I/O6 =>
I/O5 =>
I/O1 =>
I/O0 =>
80h Address Data 11h
Valid
Invalid
Invalid
Invalid
SR
70h out
81h Address Data 10h
tDBSY
Valid
Invalid
Invalid
Invalid
SR
70h out
tPROG
Valid
Invalid
Invalid
Valid
SR
70h out
IO 0 = 0, Pass
IO 0 = 1, Fail
7.6. Page Program Failure
If the Page Program operation for page address N is fail, remain data in data register may be different to input data by
host. Therefore, do not attempt to program the page address N in another block without the data input sequence. The
same input sequence of 80h command, address and data is necessary.
7.7. Restriction Multi Plane Operation
To prevent abnormal multi plane operation, do not input bad block address to all Multi Plane Operation. Otherwise, the
input data of valid block could be lost and the operation could be abnormally stopped.
Rev 1.0 / Aug. 2010
61
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