HT48C70-1(2004) データシートの表示（PDF） - Holtek Semiconductor
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HT48C70-1 Datasheet PDF : 40 Pages
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HT48R70A-1/HT48C70-1
Input/Output Ports
There are 56 bidirectional input/output lines in the
microcontroller, labeled from PA to PG, which are
mapped to the data memory of [12H], [14H], [16H],
[18H], [1AH], [1CH] and [1EH] respectively. All of these
I/O ports can be used for input and output operations.
For input operation, these ports are non-latching, that is,
the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]² (m=12H, 14H, 16H, 18H, 1AH,
1CH or 1EH). For output operation, all the data is
latched and remains unchanged until the output latch is
rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PEC, PFC, PGC) to control the input/output
configuration. With this control register, CMOS output or
Schmitt trigger input with or without pull-high resistor
structures can be reconfigured dynamically (i.e.
on-the-fly) under software control. To function as an in-
put, the corresponding latch of the control register must
write ²1². The input source also depends on the control
register. If the control register bit is ²1², the input will
read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in the ²read-modify-write² instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H, 19H, 1BH, 1DH and 1FH.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set
or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H, 18H, 1AH, 1CH or 1EH) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
There is a pull-high option available for all I/O lines (port
option). Once the pull-high option of an I/O line is se-
lected, the I/O line have pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
D a ta B u s
W r ite C o n tr o l R e g is te r
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
C o n tr o l B it
PU
DQ
CK Q
S
D a ta B it
DQ
CK Q
S
V DD
P A 0~P A 7
P B 0~P B 7
P C 0~P C 7
P D 0~P D 7
P E 0~P E 7
P F0~P F7
P G 0~P G 7
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
M
U
X
O P 0~O P 7
Input/Output Ports
Rev. 1.60
18
June 9, 2004
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