IS41C16256 データシートの表示（PDF） - Integrated Circuit Solution Inc

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IS41C16256

256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Circuit Solution Inc 

IS41C16256

IS41LV16256

AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

Symbol

tACH

tOEH

tDS

tDH

tRWC

tRWD

tCWD

tAWD

tPC

tRASP

tCPA

tPRWC

tCOH

tOFF

tWHZ

tCLCH

tCSR

tCHR

tORD

tREF

tT

Parameter

-25

-35

Min. Max. Min. Max.

Column-Address Setup Time to CAS

Precharge during WRITE Cycle

OE Hold Time from WE during

READ-MODIFY-WRITE cycle(18)

15 —

5—

15 —

8—

Data-In Setup Time(15, 22)

0— 0—

Data-In Hold Time(15, 22)

5— 6—

READ-MODIFY-WRITE Cycle Time

RAS to WE Delay Time during

READ-MODIFY-WRITE Cycle(14)

CAS to WE Delay Time(14, 20)

Column-Address to WE Delay Time(14)

65 —

35 —

17 —

21 —

80 —

45 —

25 —

30 —

EDO Page Mode READ or WRITE

Cycle Time(24)

RAS Pulse Width in EDO Page Mode

Access Time from CAS Precharge(15)

10 — 12 —

25 100K 35 100K

— 14 — 21

EDO Page Mode READ-WRITE

Cycle Time(24)

Data Output Hold after CAS LOW

32 —

5—

40 —

5—

Output Buffer Turn-Off Delay from

CAS or RAS(13,15,19, 29)

3 15

Output Disable Delay from WE

3 15

Last CAS going LOW to First CAS

10 —

returning HIGH(23)

CAS Setup Time (CBR REFRESH)(30, 20) 5 —

CAS Hold Time (CBR REFRESH)(30, 21) 7 —

OE Setup Time prior to RAS during

0—

HIDDEN REFRESH Cycle

3 15

3 15

10 —

8—

8—

0—

Refresh Period (512 Cycles)

Transition Time (Rise or Fall)(2, 3)

—8

1 50

—8

1 50

-50

Min. Max.

15 —

-60

Min. Max. Units

15 — ns

10 — 15 — ns

0—

0 — ns

8 — 10 — ns

125 — 140 — ns

70 — 80 — ns

34 —

42 —

20 —

36 — ns

49 — ns

25 — ns

50 100K

— 27

47 —

50 100K ns

— 34 ns

56 — ns

5—

3 15

5 — ns

3 15 ns

3 15

10 —

3 15 ns

10 — ns

10 —

10 —

0—

10 — ns

10 — ns

0 — ns

—8

1 50

— 8 ms

1 50 ns

AC TEST CONDITIONS

Output load:

Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)

One TTL Load and 50 pF (Vcc = 3.3V ±10%)

Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);

VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)

Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)

8

Integrated Circuit Solution Inc.

DR001-0E 01/25/2002

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