M48T212A データシートの表示（PDF） - STMicroelectronics
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M48T212A Datasheet PDF : 20 Pages
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M48T212A
Figure 2. SOIC Connections
RSTIN1
RSTIN2
RST
NC
XO
XI
NC
NC
A
NC
NC
NC
A3
A2
A1
A0
WDI
E2CON
DQ0
DQ1
DQ2
VSS
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12 M48T212A 33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
AI03048
VCC
VOUT
VCCSW
IRQ/FT
EX
NC
NC
NC
NC
NC
G
W
VBAT–
NC
E
E1CON
DQ7
DQ6
DQ5
DQ4
DQ3
VCAP
Table 1. Signal Names
A0-A3
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
XO
Oscillator Output
XI
Oscillator Input
RSTIN1
Reset 1 Input
RSTIN2
Reset 2 Input
RST
Reset Output (Open Drain)
WDI
Watchdog Input
A
Bank Select Input
E
Chip Enable Input
EX
External Chip Enable Input
G
Output Enable Input
W
Write Enable Input
E1CON
RAM Chip Enable 1 Output
E2CON
RAM Chip Enable 2 Output
IRQ/FT
Int/Freq Test Output (Open Drain)
Vccsw
VCC Switch Output
VOUT
Supply Voltage Output
VCAP
Super Capacitor Input
VBAT–
Battery Ground Pin (optional)
VCC
Supply Voltage
VSS
Ground
NC
Not Connected internally
The lithium energy source (or super capacitor)
used to permanently power the real time clock is
also used to retain RAM data in the absence of
VCC power through the VOUT pin.
The chip enable outputs to RAM (E1CON and
E2CON) are controlled during power transients to
prevent data corruption. The date is automatically
adjusted for months with less than 31 days and
corrects for leap years. The internal watchdog tim-
er provides programmable alarm windows.
The nine clock bytes (Fh - 9h and 1h) are not the
actual clock counters, they are memory locations
consisting of BiPORTTM read/write memory cells
within the static RAM array. Clock circuitry up-
dates the clock bytes with current information once
per second. The information can be accessed by
the user in the same manner as any other location
in the static memory array.
Byte 8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. Byte 7h con-
2/20
tains the watchdog timer setting. The watchdog
timer can generate either a reset or an interrupt,
depending on the state of the Watchdog Steering
bit (WDS). Bytes 6h-2h include bits that, when pro-
grammed, provide for clock alarm functionality.
Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.
The M48T212A also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the TIMEKEEPER register data and
external SRAM, providing data security in the
midst of unpredictable system operation. As VCC
falls, the control circuitry automatically switches to
the battery, maintaining data and clock operation
until valid power is restored.
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