MACH210-12 データシートの表示（PDF） - Advanced Micro Devices

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MACH210-12

High-Density EE CMOS Programmable Logic

Advanced Micro Devices 

fMAX PARAMETERS

The parameter fMAX is the maximum clock rate at which

the device is guaranteed to operate. Because the flexi-

bility inherent in programmable logic devices offers a

choice of clocked flip-flop designs, fMAX is specified for

three types of synchronous designs.

The first type of design is a state machine with feedback

signals sent off-chip. This external feedback could go

back to the device inputs, or to a second device in a

multi-chip state machine. The slowest path defining the

period is the sum of the clock-to-output time and the in-

put setup time for the external signals (tS + tCO). The re-

ciprocal, fMAX, is the maximum frequency with external

feedback or in conjunction with an equivalent speed de-

vice. This fMAX is designated “fMAX external.”

The second type of design is a single-chip state ma-

chine with internal feedback only. In this case, flip-flop

inputs are defined by the device inputs and flip-flop out-

puts. Under these conditions, the period is limited by the

internal delay from the flip-flop outputs through the inter-

nal feedback and logic to the flip-flop inputs. This fMAX is

designated “fMAX internal”. A simple internal counter is a

good example of this type of design; therefore, this pa-

rameter is sometimes called “fCNT.”

AMD

The third type of design is a simple data path applica-

tion. In this case, input data is presented to the flip-flop

and clocked through; no feedback is employed. Under

these conditions, the period is limited by the sum of the

data setup time and the data hold time (tS + tH). However,

a lower limit for the period of each fMAX type is the mini-

mum clock period (tWH + tWL). Usually, this minimum

clock period determines the period for the third fMAX, des-

ignated “fMAX no feedback.”

For devices with input registers, one additional fMAX pa-

rameter is specified: fMAXIR. Because this involves no

feedback, it is calculated the same way as fMAX no feed-

back. The minimum period will be limited either by the

sum of the setup and hold times (tSIR + tHIR) or the sum of

the clock widths (tWICL + tWICH). The clock widths are nor-

mally the limiting parameters, so that fMAXIR is specified

as 1/(tWICL + tWICH). Note that if both input and output reg-

isters are use in the same path, the overall frequency will

be limited by tICS.

All frequencies except fMAX internal are calculated from

other measured AC parameters. fMAX internal is meas-

ured directly.

CLK

CLK

LOGIC

REGISTER

(SECOND

CHIP)

LOGIC

REGISTER

tS

t CO

tS

fMAX External; 1/(tS + tCO)

CLK

LOGIC

REGISTER

fMAX Internal (fCNT)

CLK

REGISTER

LOGIC

tS

tSIR

tHIR

fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)

fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)

14128I-24

MACH210-7/10/12/15/20, Q-12/15/20

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