MAX1211ETL(2003) データシートの表示（PDF） - Maxim Integrated

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MAX1211ETL
(Rev.:2003)

65Msps, 12-Bit, IF Sampling ADC

Maxim Integrated 

65Msps, 12-Bit, IF Sampling ADC

Detailed Description

The MAX1211 uses a 10-stage, fully differential,

pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consump-

tion. Samples taken at the inputs move progressively

through the pipeline stages every half-clock cycle.

From input to output, the total clock-cycle latency is 8.5

clock cycles.

Each pipeline converter stage converts its input voltage

into a digital output code. At every stage, except the

last, the error between the input voltage and the digital

output code is multiplied and passed along to the next

pipeline stage. Digital error correction compensates for

ADC comparator offsets in each pipeline stage and

ensures no missing codes. Figure 2 shows the

MAX1211 functional diagram.

Input Track-and-Hold (T/H) Circuit

Figure 3 displays a simplified functional diagram of the

input T/H circuits. In track mode, switches S1, S2a,

S2b, S4a, S4b, S5a, and S5b are closed. The fully dif-

ferential circuits sample the input signals onto the two

capacitors (C2a and C2b) through switches S4a and

S4b. S2a and S2b set the common mode for the opera-

tional transconductance amplifier (OTA), and open

simultaneously with S1, sampling the input waveform.

Switches S4a, S4b, S5a, and S5b are then opened

before switches S3a and S3b connect capacitors C1a

and C1b to the output of the amplifier and switch S4c is

closed. The resulting differential voltages are held on

capacitors C2a and C2b. The amplifiers charge capac-

itors C1a and C1b to the same values originally held on

C2a and C2b. These values are then presented to the

first-stage quantizers and isolate the pipelines from the

fast-changing inputs. The wide input-bandwidth T/H

amplifier allows the MAX1211 to track and sample/hold

analog inputs of high frequencies well beyond Nyquist.

Analog input INP to INN can be driven either differen-

tially or single ended. For differential inputs, balance

the input impedance of INP and INN and set the com-

mon-mode voltage to midsupply (VDD/2) for optimum

performance.

Reference Output (REFOUT)

An internal bandgap reference is the basis for all the

internal voltages and bias currents used in the

MAX1211. The power-down logic input (PD) enables

and disables the reference circuit. REFOUT has

approximately 17kΩ to GND when the MAX1211 is in

power-down. The reference circuit requires 10ms to

power up and settle when power is applied to the

MAX1211 or when PD transitions from high to low.

+

T/H

∑

x2

-

FLASH

ADC

DAC

1.5 BITS

INP

T/H

INN

STAGE 1

GAIN OF 8

4 BITS

STAGE 2

GAIN OF 2

1.5 BITS

STAGE 9

GAIN OF 2

STAGE 10

END OF PIPE

1.5 BITS

1 BIT

DIGITAL ERROR CORRECTION

D0–D11

Figure 1. Pipeline Architecture—Stage Blocks

The internal bandgap reference and buffer generate

REFOUT to be 2.048V with a +100ppm/°C temperature

coefficient. Connect an external ≥0.1µF bypass capaci-

tor from REFOUT to GND for stability. REFOUT sources

up to 1.4mA and sinks up to 100µA for external circuits

with a load regulation of 35mV/mA. Short-circuit protec-

tion limits IREFOUT to a 2.1mA source current when

shorted to GND and a 240µA sink current when shorted

to VDD.

Analog Inputs and Reference

Configurations

The MAX1211 full-scale analog input range is ±VREF

with a common-mode input range of VDD / 2 ±0.5V.

VREF is the difference between VREFP and VREFN. The

MAX1211 provides three modes of reference operation.

The voltage at REFIN (VREFIN) sets the reference oper-

ation mode (Table 1).

Connect REFOUT to REFIN either with a direct short or

through a resistive divider to enter internal reference

mode. COM, REFP, and REFN are low-impedance out-

puts with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4,

and VREFN = VDD / 2 - VREFIN / 4. Bypass REFP, REFN,

and COM each with a 0.1µF capacitor in parallel with a

≥2.2µF capacitor to GND. Bypass REFP to REFN with a

10µF capacitor. Bypass REFIN and REFOUT to GND with

a 0.1µF capacitor. The REFIN input impedance is very

large (>50MΩ). When driving REFIN through a resistive

divider, use resistances ≥10kΩ to avoid loading REFOUT.

Buffered external reference mode is virtually identical to

internal reference mode except that the reference

source is derived from an external reference and not

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