MAX1211ETL(2003) データシートの表示（PDF） - Maxim Integrated

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MAX1211ETL
(Rev.:2003)

65Msps, 12-Bit, IF Sampling ADC

Maxim Integrated 

65Msps, 12-Bit, IF Sampling ADC

CLKP

CLKN

CLKTYP

CLOCK

GENERATOR

AND

DUTY CYCLE

EQUALIZER

MAX1211

VDD

GND

VDD

OVDD

INP

INP

INN

T/H

12-BIT

PIPELINE

ADC

DEC

OUTPUT

DRIVERS

D0–D11

DAV

DOR

REFOUT

REFIN

REFP

COM

REFN

G/T

INN

REFERENCE

POWER CONTROL

GND

SYSTEM

AND

PD

BIAS CIRCUITS

MAX1211

S4a

SWITCHES SHOWN IN TRACK MODE

INTERNAL

BIAS

CML

S2a

C1a S5a

C2a

S3a

OUT

S4c

S1

OTA

OUT

S4b

C2b

C1b

S3b

S2b

S5b

INTERNAL

CML

BIAS

Figure 2. Functional Diagram

Figure 3. Internal T/H Circuit

the MAX1211 REFOUT. In buffered external reference

mode, apply a stable 0.7V to 2.3V source at REFIN.

COM, REFP, and REFN are low-impedance outputs

with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and

VREFN = VDD / 2 - VREFIN / 4. Bypass REFP, REFN, and

COM each with a 0.1µF capacitor in parallel with a

≥2.2µF capacitor to GND. Bypass REFP to REFN with a

10µF capacitor. Bypass REFIN and REFOUT to GND

with a 0.1µF capacitor.

Connect REFIN to GND to enter unbuffered external

reference mode. Connecting REFIN to GND deacti-

vates the on-chip reference buffers for COM, REFP,

and REFN. With their buffers deactivated, COM, REFP,

and REFN become high-impedance inputs and must

be driven through separate, external reference

sources. Drive VCOM to VDD / 2 ±5%, and drive REFP

and REFN such that VCOM = (VREFP + VREFN) / 2. The

analog input range is ±(VREFP - VREFN). Bypass REFP,

REFN, and COM each with a 0.1µF in parallel with a

≥2.2µF capacitor to GND. Bypass REFP to REFN with a

10µF capacitor. Bypass REFOUT to GND with a 0.1µF

capacitor.

For detailed circuit suggestions and how to drive the

ADC in buffered/unbuffered external reference mode,

see the Applications Information section.

Clock Input and Clock Control Lines

(CLKP, CLKN, CLKTYP)

The MAX1211 accepts both differential and single-

ended clock inputs with a wide 20% to 80% input clock

duty cycle. For single-ended clock input operation,

connect CLKTYP to GND, CLKN to GND, and drive

CLKP with the external single-ended clock signal. To

reduce clock jitter, the external single-ended clock

must have sharp falling edges. For differential clock

input operation, connect CLKTYP to OVDD or VDD and

Table 1. Reference Modes

VREFIN

35% VREFOUT to 100% VREFOUT

0.7V to 2.3V

<0.5V

REFERENCE MODE

Internal reference mode. REFIN is driven by REFOUT either through a direct short or a resistive

divider. VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4.

Buffered external reference mode. An external 0.7V to 2.3V reference voltage is applied

to REFIN. VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4.

Unbuffered external reference mode. REFP, REFN, and COM are driven by external

reference sources. VREF is the difference between the externally applied VREFP and VREFN.

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