MAX1211ETL(2003) データシートの表示（PDF） - Maxim Integrated
部品番号
コンポーネント説明
メーカー
MAX1211ETL Datasheet PDF : 29 Pages
| |||
65Msps, 12-Bit, IF Sampling ADC
drive CLKP and CLKN with the external differential
clock signal. Consider the clock input as an analog
input and route it away from any other analog inputs
and digital signal lines.
CLKP and CLKN are high impedance when the
MAX1211 is powered down (Figure 4).
Low clock jitter is required for the specified SNR perfor-
mance of the MAX1211. Analog input sampling occurs
on the falling edge of the clock signal, requiring this
edge to have the lowest possible jitter. Jitter limits the
maximum SNR performance of any ADC according to
the following relationship:
SNR
=
20
×
log
2
×
π
1
× fIN
×
tJ
where fIN represents the analog input frequency and tJ
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 65.1dB of SNR with an input fre-
quency of 250MHz, the system must have less than
0.35ps of clock jitter. In actuality, there are other noise
sources such as thermal noise and quantization noise
that contribute to the system noise requiring the clock
jitter to be less than 0.22ps to obtain the specified
65.1dB of SNR at 250MHz.
System Timing Requirements
Figure 5 shows the relationship between the clock, ana-
log inputs, DAV indicator, DOR indicator, and the result-
ing output data. The analog input is sampled on the
falling edge of the clock signal and the resulting data
appears at the digital outputs 8.5 clock cycles later.
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
cuitry may be latched with the falling edge of the clock.
Data Valid Output (DAV)
DAV is a single-ended version of the input clock that is
compensated to correct for any input clock duty-cycle
variations. The output data changes on the falling edge
of DAV, and DAV rises once the output data is valid.
The falling edge of DAV is synchronized to have a
6.4ns delay from the falling edge of the input clock.
Output data at D0–D11 and DOR are valid from 8.4ns
before the rising edge of DAV to 6.6ns after the rising
edge of DAV.
DAV is high impedance when the MAX1211 is in power-
down (PD = high). DAV is capable of sinking and sourc-
ing 600µA and has three times the drive strength of
VDD
CLKP
CLKN
GND
S1H
10kΩ
MAX1211
10kΩ S2H
S1L
10kΩ
DUTY-
CYCLE
EQUALIZER
10kΩ
SWITCHES S1_ AND S2_ ARE OPEN
DURING POWER-DOWN, MAKING
S2L
CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S2_ ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
Figure 4. Simplified Clock Input Circuit
D0–D11 and DOR. It is typically used to latch the
MAX1211 output data into an external back-end digital
circuit.
Keep the capacitive load on DAV as low as possible
(<25pF) to avoid large digital currents feeding back into
the analog portion of the MAX1211 and degrading its
dynamic performance. An external buffer on DAV iso-
lates it from heavy capacitive loads. Refer to the
MAX1211 EV kit schematic for an example of DAV dri-
ving back-end digital circuitry through an external buffer.
Data Out-of-Range Indicator (DOR)
The DOR digital output indicates when the analog input
voltage is out of range. When DOR is high, the analog
input is out of range. When DOR is low, the analog
input is within range. The valid differential input range is
from (VREFP - VREFN) to (VREFN - VREFP). Signals out-
side this valid differential range cause DOR to assert
high as shown in Table 2.
DOR is synchronized with DAV and transitions along
with output data D0–D11. There is an 8.5 clock-cycle
latency in the DOR function just as with the output data
(Figure 5).
DOR is high impedance when the MAX1211 is in
power-down (PD = high). DOR enters a high-imped-
______________________________________________________________________________________ 19
Share Link: 