MAX12559ETKD データシートの表示（PDF） - Maxim Integrated

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MAX12559ETKD

Dual, 96Msps, 14-Bit, IF/Baseband ADC

Maxim Integrated 

Dual, 96Msps, 14-Bit, IF/Baseband ADC

Pin Description (continued)

PIN

NAME

FUNCTION

Power-Down Digital Input.

65

PD

PD = GND: ADCs are fully operational.

PD = OVDD: ADCs are powered down.

Shared Reference Digital Input.

SHREF = VDD: Shared reference enabled.

66

SHREF SHREF = GND: Shared reference disabled.

When sharing the reference, externally connect REFAP and REFBP together to ensure that VREFAP =

VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure

that VREFAN = VREFBN.

Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA.

For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from

67

REFOUT REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥ 0.1µF capacitor.

For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥ 0.1µF

capacitor.

Single-Ended Reference Analog Input. For internal reference and buffered external reference operation,

apply a 0.7V to 2.3V DC reference voltage to REFIN. Bypass REFIN to GND with a 4.7µF capacitor.

68

REFIN

Within its specified operating voltage, REFIN has a > 50MΩ input impedance, and the differential

reference voltage (VREF_P - VREF_N) is generated from REFIN. For unbuffered external reference

operation, connect REFIN to GND. In this mode, REF_P, REF_N, and COM_ are high-impedance inputs

that accept the external reference voltages.

—

EP

Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve the

specified dynamic performance.

MAX12559

FLASH

ADC

+Σ

x2

−

DAC

IN_P

STAGE 10

IN_N

STAGE 1

STAGE 2

STAGE 9

END OF PIPELINE

DIGITAL ERROR CORRECTION

D0_ THROUGH D13_

Figure 1. Pipeline Architecture—Stage Blocks

Detailed Description

The MAX12559 uses a 10-stage, fully differential,

pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consump-

tion. Samples taken at the inputs move progressively

through the pipeline stages every half clock cycle.

From input to output the total latency is 8 clock cycles.

Each pipeline converter stage converts its input voltage

to a digital output code. At every stage, except the last,

the error between the input voltage and the digital out-

put code is multiplied and passed on to the next

pipeline stage. Digital error correction compensates for

ADC comparator offsets in each pipeline stage and

ensures no missing codes. Figure 2 shows the

MAX12559 functional diagram.

14 ______________________________________________________________________________________

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