MAX15048 データシートの表示（PDF） - Maxim Integrated

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MAX15048

Triple-Output Buck Controllers with Tracking/Sequencing

Maxim Integrated 

MAX15048/MAX15049

Triple-Output Buck Controllers

with Tracking/Sequencing

Use the following equations to calculate the required

ESR, ESL, and capacitance value during a load step:

ESR = ∆VESR

I STEP

COUT = ISTEP × t RESPONSE

∆VQ

ESL = ∆VESL × t STEP

I STEP

t RESPONSE

=

1

3 × fCO

where ISTEP is the load step, tSTEP is the rise time of the

load step, tRESPONSE is the response time of the con-

troller, and fCO is the closed-loop crossover frequency

of system (see the Compensation Design Guidelines

section).

Setting the Current Limit

The MAX15048/MAX15049 use a valley current-sense

method for current limiting. The valley current-limit

threshold (VLIM) is internally set at 69mV (typ).

The voltage drop across the low-side MOSFET due to its

on-resistance is used to sense the inductor current. The

voltage drop (VVALLEY) across the low-side MOSFET at

the valley point and at ILOAD is:

V= VALLEY

RDS(ON)

×

(ILOAD(MAX)

-

∆IP-P

2

)

RDS(ON) is the on-resistance of the low-side MOSFET,

ILOAD is the rated load current, and DIP-P is the peak-to-

peak inductor current.

The RDS(ON) of the MOSFET varies with temperature.

Calculate the RDS(ON) of the MOSFET at its operating

junction temperature at full load using its data sheet. To

compensate for this temperature variation, the current-

limit circuitry has a temperature coefficient of 3333ppm/NC.

This allows the valley current-limit threshold (VLIM) to

track and partially compensate for the increase in the

RDS(ON) of the synchronous MOSFET with increasing

temperature.

Power-MOSFET Selection

When choosing the n-channel MOSFETs, consider the

total gate charge, RDS(ON), power dissipation, the

maximum drain-to-source voltage, and package thermal

impedance. The product of the MOSFET gate charge

and on-resistance is a figure of merit, with a lower num-

ber signifying better performance. Choose MOSFETs that

are optimized for high-frequency switching applications.

The average gate-drive current from the MAX15048/

MAX15049s’ output is proportional to the frequency and

gate charge required to drive the MOSFET. The power

dissipated in the MAX15048/MAX15049 is proportional

to the input voltage and the average drive current (see

the Power Dissipation section).

Compensation Design Guidelines

The MAX15048/MAX15049 use a fixed-frequency, volt-

age-mode control scheme that regulates the output

voltage by differentially comparing the “sampled” out-

put voltage against a fixed reference. The subsequent

“error” voltage—that appears at the error-amplifier output

(COMP_)—is compared against an internal ramp voltage

to generate the required duty cycle of the pulse-width

modulator. A 2nd-order lowpass LC filter removes the

switching harmonics and passes the DC component of

the pulse-width-modulated signal to the output. The LC

filter, which has an attenuation slope of -40dB/decade,

introduces 180° out-of-phase shift at frequencies above

the LC resonant frequency. This phase shift, in addi-

tion to the inherent 180° of phase shift of the regulator’s

self-governing (negative) feedback system, poses the

potential for positive feedback. The error amplifier and

its associated circuitry are designed to compensate for

this instability in order to achieve a stable closed-loop

system.

The basic regulator loop consists of a power modula-

tor (comprising the regulator’s pulse-width modulator,

associated circuitry, and LC filter), an output feedback

divider, and an error amplifier. The power modulator has

a DC gain set by VIN/VRAMP, with a double pole and a

single zero set by the output inductance (L), the output

capacitance (COUT), and its ESR. A second, higher fre-

quency zero also exists, which is a function of the output

capacitor’s ESR and ESL, though only taken into account

when using very high-quality filter components and/or

frequencies of operation.

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