MAX5102BEUE データシートの表示（PDF） - Maxim Integrated

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MAX5102BEUE

+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs

Maxim Integrated 

+2.7V to +5.5V, Low-Power, Dual, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

ELECTRICAL CHARACTERISTICS (continued)

(VDD = VREF = +2.7V to +5.5V, GND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at

VDD = VREF = +3V and TA = +25°C.)

PARAMETER

DYNAMIC PERFORMANCE

Output Voltage Slew Rate

Output Settling Time (Note 3)

SYMBOL

CONDITIONS

From code 00 to code F0 hex

To 1/2LSB, from code 00 to code F0 hex

MIN TYP MAX UNITS

0.6

V/µs

6

µs

Channel-to-Channel Isolation

(Note 4)

Code 00 to code FF hex

500

nVs

Digital Feedthrough (Note 5)

Code 00 to code FF hex

0.5

nVs

Digital-to-Analog Glitch Impulse

Code 80 hex to code 7F hex

90

nVs

Signal-to-Noise plus Distortion

Ratio

SINAD

Multiplying Bandwidth

Wideband Amplifier Noise

Shutdown Recovery Time

Time to Shutdown

POWER SUPPLIES

tSDR

tSDN

Power-Supply Voltage

VDD

Supply Current (Note 6)

IDD

Shutdown Current

DIGITAL TIMING (Figure 1) (Note 7)

Address to WR Setup

tAS

Address to WR Hold

tAH

Data to WR Setup

tDS

Data to WR Hold

tDH

WR Pulse Width

tWR

REF = 2.5Vp-p at 1kHz, VREF(DC) = 1.5V,

VDD = 3V, code FF hex

REF = 2.5Vp-p at 10kHz, VREF(DC) = 1.5V,

VDD = 3V, code FF hex

REF = 0.5Vp-p, VREF(DC) = 1.5V,

VDD = 3V, -3dB bandwidth

To ±1/2LSB of final value of VOUT

IDD < 5µA

70

dB

60

650

kHz

60

µVRMS

13

µs

20

µs

2.7

5.5

V

190

360

µA

0.001

1

µA

5

ns

0

ns

25

ns

0

ns

20

ns

Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.

Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VREF]. Where VF0,meas is the DAC output voltage with input code F0 hex,

and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VREF · 240 / 256).

Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of VOUT’s final value.

Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any

other DAC output. The measured channel has a fixed code of 80 hex.

Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight

data inputs with WR at VDD.

Note 6: RL = ∞, digital inputs at GND or VDD.

Note 7: Timing measurement reference level is (VIH + VIL) / 2.

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