MAX5104 データシートの表示（PDF） - Maxim Integrated

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MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface

Maxim Integrated 

Low-Power, Dual, Voltage-Output, 12-Bit DAC

with Serial Interface

+5V

DIN

MAX5104 SCLK

CS

SS

MOSI

SCK

SPI/QSPI

PORT

I/O

CPOL = 0, CPHA = 0

Figure 3. Connections for SPI/QSPI

MSB...................................................................................LSB

16 Bits of Serial Data

Address Bits

Control Bits

MSB...Data Bits...LSB

Sub

Bit

A0

C1, C0

1 Address/2 Control Bits

D11.......................D0 S0

12 Data Bits

0

Figure 4. Serial-Data Format

The MAX5104’s digital inputs are double buffered,

which allows any of the following: loading the input reg-

ister(s) without updating the DAC register(s), updating

the DAC register(s) from the input register(s), or updating

the input and DAC registers concurrently. The address

and control bits allow the DACs to act independently.

Send the 16-bit data as one 16-bit word (QSPI) or two

8-bit packets (SPI, MICROWIRE), with CS low during

this period. The address and control bits determine

which register will be updated, and the state of the reg-

isters when exiting power-down. The 3-bit address/con-

trol determines the following:

• Registers to be updated

• Clock edge on which data is to be clocked out via the

serial-data output (DOUT)

• State of the user-programmable logic output

• Configuration of the device after power-down

The general timing diagram of Figure 5 illustrates how

data is acquired. Driving CS low enables the device to

receive data; otherwise, the interface control circuitry is

disabled. With CS low, data at DIN is clocked into the

register on the rising edge of SCLK. As CS goes high,

data is latched into the input and/or DAC registers,

depending on the address and control bits. The maximum

clock frequency guaranteed for proper operation is

10MHz. Figure 6 shows a more detailed timing diagram

of the serial interface.

CS

SCLK

DIN

1

8

A0

C1 C0 D11 D10 D9 D8 D7

9

16

D6

D5 D4 D3 D2 D1 D0 S0

COMMAND

EXECUTED

Figure 5. Serial-Interface Timing Diagram

8 _______________________________________________________________________________________

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