MAX7032 データシートの表示（PDF） - Maxim Integrated

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MAX7032

Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL

Maxim Integrated 

Low-Cost, Crystal-Based, Programmable,

ASK/FSK Transceiver with Fractional-N PLL

Table 4. Register Configuration

NAME (ADDRESS)

POWER[7:0] (0x00)

CONTRL[7:0] (0x01)

CONF0[7:0] (0x02)

CONF1[7:0] (0x03)

OSC[7:0] (0x05)

tOFF[15:8] (0x06)

tOFF[7:0] (0x07)

tCPU[7:0] (0x08)

tRF[15:8] (0x09)

tRF[7:0] (0x0A)

tON[15:8] (0x0B)

tON[7:0] (0x0C)

TxLOW[15:8] (0x0D)

TxLOW[7:0] (0x0E)

TxHIGH[15:8] (0x0F)

TxHIGH[7:0] (0x10)

STATUS[7:0] (0x1A)

D7

LNA

AGCLK

MODE

X

OSC7

tOFF 15

tOFF 7

tCPU 7

tRF 15

tRF 7

tON 15

tON 7

TxL15

TxL7

TxH15

TxH7

LCKD

D6

AGC

GAIN

T/R

ACAL

OSC6

tOFF 14

tOFF 6

tCPU 6

tRF 14

tRF 6

tON 14

tON 6

TxL14

TxL6

TxH14

TxH6

GAINS

D5

MIXER

TRK_EN

MGAIN

CLKOF

OSC5

tOFF 13

tOFF 5

tCPU 5

tRF 13

tRF 5

tON 13

tON 5

TxL13

TxL5

TxH13

TxH5

CLKON

DATA

D4

D3

BaseB

PkDet

X

PCAL

DRX

OFPS1

CDIV1

CDIV0

OSC4

OSC3

tOFF 12

tOFF 4

tCPU 4

tRF 12

tRF 4

tON 12

tON 4

TxL12

tOFF 11

tOFF 3

tCPU 3

tRF 11

tRF 3

tON 11

tON 3

TxL11

TxL4

TxL3

TxH12

TxH11

TxH4

TxH3

0

0

D2

PA

FCAL

OFPS0

DT2

OSC2

tOFF 10

tOFF 2

tCPU 2

tRF 10

tRF 2

tON 10

tON 2

TxL10

TxL2

TxH10

TxH2

0

D1

RSSIO

CKOUT

ONPS1

DT1

OSC1

tOFF 9

tOFF 1

tCPU 1

tRF 9

tRF 1

tON 9

tON 1

TxL9

TxL1

TxH9

TxH1

PCALD

D0

X

SLEEP

ONPS0

DT0

OSC0

tOFF 8

tOFF 0

tCPU 0

tRF 8

tRF 0

tON 8

tON 0

TxL8

TxL0

TxH8

TxH0

FCALD

Continuous Receive Mode (DRX = 0)

In continuous receive mode, individual analog modules

can be powered on directly through the power configu-

ration register (register 0x00). The SLEEP bit (bit 0 in

register 0x01) overrides the power configuration regis-

ters and puts the device into deep-sleep mode when

set. It is also necessary to write the frequency divisor of

the external crystal in the oscillator frequency register

(register 0x05) to optimize image rejection and to

enable accurate calibration sequences for the polling

timer and the FSK demodulator. This number is the

integer result of fXTAL/100kHz.

If the FSK receive function is selected, it is necessary to

perform an FSK calibration to allow operation; other-

wise, the demodulator is saturated. Polling timer cali-

bration is not necessary. See the Calibration section for

more information.

Discontinuous Receive Mode (DRX = 1)

In the discontinuous receive mode (DRX = 1), the

receiver modules set to logic 1 by the power register

(0x00) of the MAX7032 toggle between OFF and ON,

according to internal timers tOFF, tCPU, tRF, and tON. It

is also necessary to write the frequency divisor of the

external crystal in the oscillator frequency register (reg-

ister 0x05). This number is the integer result of

fXTAL/100kHz. Before entering the discontinuous

receive mode for the first time, it is also necessary to

calibrate the timers (see the Calibration section).

The MAX7032 uses a series of internal timers (tOFF,

tCPU, tRF, and tON) to control its power-up sequence.

The timer sequence begins when both CS and DIO are

one. The MAX7032 has an internal pullup on the DIO

pin, so the user must tri-state the DIO line when CS

goes high.

The external CPU can then go to a sleep mode during

tOFF. A high-to-low transition on DIO or a low level on

DIO serves as the wake-up signal for the CPU, which

must then start its wake-up procedure and drive DIO

low before tLOW expires (tCPU + tRF + tON). Once tRF

expires and tON is active, the MAX7032 enables the

data output. The CPU must then keep DIO low for as

long as it may need to analyze any received data.

Releasing DIO after tON expires causes the MAX7032

to pull up DIO, reinitiating the tOFF timer.

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