M7010R データシートの表示（PDF） - STMicroelectronics
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M7010R Datasheet PDF : 67 Pages
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M7010R
Table 7. AC Timing Parameters with CLK2X
M7010R-066
Row Symbol
Min Max
M7010R-083
Unit
Min Max
Description(1)
1
fCLK
133
166 MHz CLK2X frequency
2
tCLK
7.5
6.0
ns CLK2X period
3
tCKHI
3.0
2.4
ns CLK2X high pulse(2)
4
tCKLO
3.0
2.4
ns CLK2X low pulse(2)
5
tISCH
2.5
1.8
ns Input Setup Time to CLK2X rising edge(2)
6
tIHCH
0.6
0.6
ns Input Hold Time to CLK2X rising edge(2)
7
tICSCH
4.2
3.5
ns Cascaded Input Setup Time to CLK2X rising edge(2)
8
tICHCH
0.6
0.6
ns Cascaded Input Hold Time to CLK2X rising edge(2)
9
tCKHOV
8.5
7.0 ns Rising edge of CLK2X to LHO, FULO, BHO, FULL valid(3)
10 tCKHDV
9.0
7.5 ns Rising edge of CLK2X to DQ valid(4)
11 tCKHDZ
8.5
7.0 ns Rising edge of CLK2X to DQ high-Z(5)
12 tCKHSV
9.0
7.5 ns Rising edge of CLK2X to SRAM Bus valid(4)
13 tCKHSHZ
6.5
6.0 ns Rising edge of CLK2X to SRAM Bus high-Z(4,5)
14 tCKHSLZ 7.0
6.5
ns Rising edge of CLK2X to SRAM Bus low-Z(4,5)
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VDD = 1.8V.
2. Values are based on 50% signal levels.
3. Based on an AC load of CL = 50pF (see Figure 5, page 12 and Figure 8, page 12).
4. Unless otherwise noted, all values are based on AC load of CL = 50pF (see Figure 5, page 12 and Figure 8, page 12).
5. These parameters are sampled and not 100% tested.
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