M68AR024D データシートの表示（PDF） - STMicroelectronics

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M68AR024D

16 Mbit (1M x16) 1.8V Asynchronous SRAM

STMicroelectronics 

M68AR024D

Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms

1.95V

VCC

1.65V

VDR > 1.0V

E1

DATA RETENTION MODE

tCDR

E1 ≥ VDR – 0.2V

tR

AI05855

Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms

1.95V

VCC

1.65V

VDR > 1.0V

E2

DATA RETENTION MODE

tCDR

E2 ≤ 0.2V

tR

AI05875

Table 9. Low VCC Data Retention Characteristics

Symbol

Parameter

Test Condition

Min Typ Max

ICCDR (1) Supply Current (Data Retention)

VCC = 1.0V, E1 ≥ VCCQ –0.2V OR

E2 ≤ 0.2V OR

UB, LB ≥ VCCQ –0.2V,

f=0

0.5

5

tCDR (2)

Chip deselected to Data

Retention Time

0

tR (2) Operation Recovery Time

tAVAV

E1 ≥ VCCQ –0.2V OR

VDR (1) Supply Voltage (Data Retention)

E2 ≤ 0.2V OR

UB, LB ≥ VCCQ –0.2V,

1.0

f=0

Note: 1. All other Inputs at VIH ≥ VCCQ –0.2V or VIL ≤ 0.2V.

2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time.

3. No input may exceed VCC +0.2V.

Unit

µA

ns

ns

V

14/19

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