M69AR024BL80ZB8T データシートの表示（PDF） - STMicroelectronics
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M69AR024BL80ZB8T Datasheet PDF : 28 Pages
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M69AR024B
M69AR024B
Symbol Alt.
Parameter
-70, -80
Unit
Min
Max
tGHEL (6) tOHCL Output Enable High to Chip Enable Low
–5
ns
tWHAX (4) tWR Write Enable High to Address Transition
15
1000
ns
tWHDZ
tDH Write Enable High to Input Hi-Z
0
ns
tWLBH (3) tWP Write Enable Low to LB, UB High
65
ns
tWLWH (3) tWP Write Enable Low to Write Enable High
65
1000
ns
Note: 1. Maximum value is applicable if E1 is kept at Low without any address change. If needed by system operation, please contact your
local ST representative for relaxation of the 1000ns limitation.
2. Minimum value must be equal to or greater than the sum of write pulse (tELEH, tWLWH or tBLBH) and write recovery time (tWRC, tWR
or tBR).
3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last.
4. Write recovery is defined from Write pulse is defined from the rising edge of E1, W, or LB/UB, whichever occurs first.
5. Applicable to any address change when E1 stays Low.
6. If G is Low after minimum tGHEL, the read cycle is initiated. In other words, G must be brought High within 5ns after E1 is brought
Low. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
7. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before
new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
8. Applicable for Byte mask only. Byte mask setup time is defined to the High to Low transition of E1 or W whichever occurs last.
9. Applicable for Byte mask only. Byte mask hold time is defined from the Low to High transition of E1 or W whichever occurs first.
Figure 10. Chip Enable Controlled, Write AC Waveforms
A0-A19
tAVEL
E1
tAVWL
W
LB, UB
G
tAVBL
tGHEL
DQ0-DQ15
Note: E2 = High.
tELAX
ADDRESS VALID
tELEH
tEHAX
tWLWH
tWHAX
tBLBH
tBHAX
tAVEL
tAVWL
tAVBL
tDVEH
tDVWH
tDVBH
VALID DATA INPUT
tEHDZ
tWHDZ
tBHDZ
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