MC33910G5AC/MC3433910G5AC
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
tBIT
tBIT
VLIN_REC
THREC(MAX) 74.4% VSUP
LIN
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
58.1% VSUP
42.2% VSUP
28.4% VSUP
RXD
Output of receiving Node 1
tREC_PDF(1)
RXD
Output of receiving Node 2
tBUS_DOM(MAX)
tBUS_REC(MIN)
tBUS_DOM(MIN)
tBUS_REC(MAX)
tREC_PDR(1)
tREC_PDR(2)
tREC_PDF(2)
Figure 7. LIN Timing Measurements for Normal Slew Rate
TXD
tBIT
tBIT
VLIN_REC
THREC(MAX) 77.8% VSUP
LIN
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
61.6% VSUP
38.9% VSUP
25.1% VSUP
RXD
Output of receiving Node 1
tREC_PDF(1)
RXD
Output of receiving Node 2
tBUS_DOM(MAX)
tBUS_REC(MIN)
tBUS_DOM(MIN)
tBUS_REC(MAX)
tREC_PDR(1)
tREC_PDR(2)
tREC_PDF(2)
Figure 8. LIN Timing Measurements for Slow Slew Rate
Thresholds of
receiving node 1
Thresholds of
receiving node 2
Thresholds of
receiving node 1
Thresholds of
receiving node 2
Analog Integrated Circuit Device Data
Freescale Semiconductor
33910
21