MT47H128 データシートの表示（PDF） - Micron Technology

部品番号

コンポーネント説明

メーカー

MT47H128

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

Figure 73: WRITE-to-Power-Down or Self Refresh Entry

CK#

CK

Command

T0

WRITE

CKE

Address

A10

DQS, DQS#

DQ

Valid

T1

T2

NOP

NOP

T3

T4

NOP

Valid

T5

Valid

T6

Valid

T7

NOP1

T8

tCKE (MIN)

WL = 3

DO DO DO DO

tWTR

Power-down or

self refresh entry1

Transitioning Data

Don’t Care

Note: 1. Power-down or self refresh entry may occur after the WRITE burst completes.

Figure 74: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry

CK#

T0

T1

T2

T3

T4

T5

Ta0

Ta1

Ta2

CK

Command WRITE

NOP

NOP

NOP

Valid

Valid

Valid1

NOP

tCKE (MIN)

CKE

Address

A10

DQS, DQS#

DQ

Valid

WL = 3

DO DO DO DO

WR2

Indicates a break in

time scale

Power-down or

self refresh entry

Transitioning Data

Don’t Care

Notes:

1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may oc-

cur 1 x tCK later at Ta1, prior to tRP being satisfied.

2. WR is programmed through MR9–MR11 and represents (tWR [MIN] ns/tCK) rounded up

to next integer tCK.

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

121

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2007 Micron Technology, Inc. All rights reserved.

Share Link: