MT47H128 データシートの表示（PDF） - Micron Technology

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MT47H128

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

Figure 4: 128 Meg x 8 Functional Block Diagram

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Block Diagrams

ODT

CKE

CK

CK#

CS#

RAS#

CAS#

WE#

Control

logic

Mode

registers

17

A[13:0],

BA[2:0]

17

Address

register

Refresh

counter

14

14

3

10

14

Row-

address

MUX

Bank 7

Bank 7

Bank 6

Bank 6

Bank 5

Bank 5

Bank 4

Bank 4

Bank 3

Bank 3

Bank 2

Bank 2

Bank 1

Bank 1

Bank 0

Bank 0

row-

address

latch

16,384

Memory array

(16,384 x 256 x 32)

and

decoder

Sense amplifers

8192

32

2

Bank

control

logic

I/O gating

DM mask logic

256

(x32)

COL0, COL1

CK, CK#

8

32 Read

latch

8

8

8

MUX

8

Data

DLL

DRVRS

DQS

2

generator UDQS, UDQS#

Input LDQS, LDQS#

registers

2

2

WRITE

FIFO

32

and

drivers

2

42

Mask 2

8

2

22

2

RCVRS

8

Column- 8

address

counter/

2

latch

Column

decoder

CK,CK#

CK out

CK in

32 8

Data 8

8

COL0, COL1

88

8

8

2

ODT control

sw1 sw2 sw3

VDDQ

sw1 sw2 sw3

R1 R2 R3

R1 R2 R3

sw1 sw2 sw3

R1 R2 R3

R1 R2 R3

sw1 sw2 sw3

R1 R2 R3

R1 R2 R3

VSSQ

DQ[7:0]

DQS, DQS#

RDQS#

RDQS

DM

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

12

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© 2007 Micron Technology, Inc. All rights reserved.

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