MT46V128M4 データシートの表示（PDF） - Micron Technology
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MT46V128M4 Datasheet PDF : 91 Pages
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512Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 13:
Clock Input Operating Conditions
Notes: 1–5, 16, 17, 31 apply to the entire table; Notes appear on page 35;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V (VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V for -5B)
Parameter/Condition
Clock input mid-point voltage: CK and CK#
Clock input voltage level: CK and CK#
Clock input differential voltage: CK and CK#
Clock input differential voltage: CK and CK#
Clock input crossing point voltage: CK and CK#
Symbol
VMP(DC)
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
Min
1.15
–0.3
0.36
0.7
0.5 × VDDQ - 0.2
Max
1.35
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 × VDDQ + 0.2
Units
V
V
V
V
V
Notes
7, 10
7
7, 9
9
10
Figure 11: SSTL_2 Clock Input
2.80V
Maximum clock level1
CK#
1.45V
1.25V
1.05V
X
X
VMP(DC)2 VIX(AC)3 VID(DC)V4ID(AC)5
CK
–0.30V
Minimum clock level1
Notes:
1. CK or CK# may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
2. This provides a minimum of 1.15V to a maximum of 1.35V and is always half of VDDQ.
3. CK and CK# must cross in this region.
4. CK and CK# must meet at least VID(DC) MIN when static and is centered around VMP(DC).
5. CK and CK# must have a minimum 700mV peak-to-peak swing.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values for all devices other than -5B.
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
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