MX25L12805D データシートの表示（PDF） - Unspecified
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MX25L12805D Datasheet PDF : 42 Pages
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MX25L12805D
Table 2. COMMAND DEFINITION
COMMAND
(byte)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
WREN (write WRDI (write
enable)
disable)
06 (hex
04 (hex)
sets the
(WEL) write
enable latch
bit
resets the
(WEL) write
enable latch
bit
RDID (read RDSR (read
identification) status
register)
9F (hex)
05 (hex)
outputs
to read out
JEDEC ID: 1- the values of
byte
the status
manufacturer register
ID & 2-byte
device ID
WRSR (write
status
register)
01 (hex)
to write new
values to the
status
register
READ (read
data)
03 (hex)
AD1
AD2
AD3
n bytes read
out until CS#
goes high
FAST READ
(fast read
data)
0B (hex)
AD1
AD2
AD3
X
n bytes read
out until CS#
goes high
SE (Sector
erase)
20 (hex)
AD1
AD2
AD3
to erase the
selected
sector
COMMAND BE (block
(byte)
erase)
CE (chip erase) PP (Page
program)
DP (Deep
power down)
RDP (Release RES (read
from deep
electronic ID)
power down)
REMS (read
electronic
manufacturer &
device ID)
1st byte
D8 (hex)
60 or C7 (hex) 02 (hex)
B9 (hex)
AB (hex)
2nd byte
AD1
AD1
3rd byte
AD2
AD2
4th byte
AD3
AD3
5th byte
Action
to erase the to erase whole to program the enters deep release from
selected block chip
selected page power down deep power
mode
down mode
Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first
AB (hex)
x
x
x
90 (hex)
x
x
ADD(note 1)
to read out 1- outout the
byte device ID manufacturer ID
& device ID
COMMAND
(byte)
ENSO (enter
secured OTP)
EXSO (exit secured RDSCUR (read
OTP)
security register)
WRSCUR (write
security register)
1st byte
B1 (hex)
C1 (hex)
2B (hex)
2F (hex)
2nd byte
3rd byte
4th byte
5th byte
Action
to enter the 512-bit to exit the 512-bit to read value of
secured OTP mode secured OTP mode security register
to set the lock-down
bit as "1" (once
lock-down, cannot
be updated)
Note 2: It is not recommoded to adopt any other code not in the command definition table, which will potentially emter the hidden mode.
P/N: PM1310
REV. 1.1, OCT. 01, 2008
9
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