M80C196KB データシートの表示（PDF） - Intel

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M80C196KB

16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER

Intel 

M80C196KB

M80C196KB FUNCTIONAL

DEVIATIONS

The M80C196KB has the following problems

1 The DJNZW instruction is guaranteed to be func-

tional The DJNZ (byte instruction) work around is

no longer needed

2 The serial port only tolerates a a1 25% b7 5%

baud rate error between Transmitter and Receiv-

er If the serial port fails on the receiver increase

the baud rate

3 The HSI unit has two errata one dealing with res-

olution and the other with first entries into the

FIFO

The HSI resolution is 9 states instead of 8 states

Events on the same line may be lost if they occur

faster than once every 9 state times

There is a mismatch between the 9 state time HSI

resolution and the 8 state time timer This causes

one time value to be unused every 9 timer counts

Events may receive a time-tag one count later

than expected because of this ‘‘skipped’’ time val-

ue

If the first two events into an empty FIFO (not

including the Holding Register) occur in the same

internal phase both are recorded with one time-

tag Otherwise if the second event occurs within

9 states after the first its time-tag is one count

later than the first’s If this is the ‘‘skipped’’ time

value the second event’s time-tag is 2 counts lat-

er than the first’s

If the FIFO and Holding Register are empty the

first event will transfer into the Holding Register

after 8 state times leaving the FIFO empty again

If the second event occurs after this time it will

act as a new first event into an empty FIFO

4 The serial port Framing Error flag that failed to in-

dicate an error if the bit preceding the stop bit is a

1 has been fixed

CONVERTING FROM OTHER M8097

FAMILY PRODUCTS TO THE

M80C196KB

The following list of suggestions for designing an

M809XBH system will yield a design that is easily

converted to the M80C196KB

1 Do not base critical timing loops on instruction or

peripheral execution times

2 Use equate statements to set all timing parame-

ters including the baud rate

3 Do not base hardware timings on CLKOUT or

XTAL1 The timings of the M80C196KB are differ-

ent than those of the M8X9XBH but they will

function with standard ROM EPROM Peripheral

type memory systems

4 Make sure all inputs are tied high or low and not

left floating

5 Indexed and indirect operations relative to the

stack pointer (SP) work differently on the

M80C196KB than on the M8097 On the M8097

the address is calculated based on the un-updat-

ed version of the stack pointer The M80C196KB

uses the updated version The offset for

PUSH SP POP SP PUSH nn SP and POP

nn SP instructions may need to be changed by a

count of 2

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