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SAB83C166W-5M データシートの表示(PDF) - Infineon Technologies

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SAB83C166W-5M Datasheet PDF : 67 Pages
First Prev 61 62 63 64 65 66 67
SAB 80C166W/83C166W
AC Characteristics (cont’d)
CLKOUT and READY
VCC = 5 V ± 10 %; VSS = 0 V
TA = 0 to + 70 ˚C for SAB 83C166W-5M, SAB 80C166W/83C166W-M
TA = – 40 to + 85 ˚C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3
TA = – 40 to + 110 ˚C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4
CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
Parameter
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Synchronous READY
setup time to CLKOUT
Synchronous READY
hold time after CLKOUT
Asynchronous READY
low time
Asynchronous READY
setup time 1)
Asynchronous READY
hold time 1)
Async. READY hold time
after RD, WR high
(Demultiplexed Bus) 2)
Symbol CPU Clock = 16 MHz Variable CPU Clock
Duty cycle 0.4 to 0.6
1/TCLP = 1 to 20 MHz
min.
max.
min.
max.
t29 CC 62.5
t30 CC 15
t31 CC 15
t32 CC –
t33 CC –
t34 CC 0 + tA
62.5
5
5
10 + tA
TCLP
TCLmin – 10
TCLmin – 10
0 + tA
TCLP
5
5
10 + tA
t35 SR 10
10
t36 SR 10
10
t37 SR 77.5
TCLP + 15
t58 SR 20
20
t59 SR 0
0
t60 SR 0
0
0
+ 2tA + tF
2)
TCL - 25
+ 2tA + tF
2)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
Semiconductor Group
63

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