SC4602A データシートの表示（PDF） - Semtech Corporation
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SC4602A Datasheet PDF : 18 Pages
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SC4602A/B
POWER MANAGEMENT
Applications Information (Cont.)
Where:
R = load resistance and
RC = C4’s ESR.
The design guidelines for the SC4602A/B applications
are as following:
The compensation network will have the characteristic
as follows:
Where:
1+ s 1+ s
GCOMP (s)
=
ωI
s
⋅
1+
ωZ1
s
⋅
⋅
1
+
ωZ2
s
ωP1
ωP2
1
ωI = R7 ⋅ (C1 + C2 )
1
ωZ1 = R1 ⋅ C2
1
ωZ2 = (R7 + R8 ) ⋅ C9
ωP1
=
C1 + C2
R1 ⋅ C1 ⋅ C2
1
ωP2 = R8 ⋅ C9
After the compensation, the converter will have the fol-
lowing loop gain:
1. Set the loop gain crossover corner frequency ωC for
given switching corner frequency ωS =2pfs,
2. Place an integrator at the origin to increase DC and
low frequency gains,
3. Select ωZ1 and ωZ2 such that they are placed near
ωO to damp the peaking and the loop gain has a
-20dB/dec rate to go across the 0dB line for
obtaining a wide bandwidth,
4. Cancel the zero from C4’s ESR by a compensator
pole ωP1 (ωP1 = ωESR = 1/( RCC4)),
5. Place a high frequency compensator pole ωp2 (ωp2
= pf ) to get the maximum attenuation of the
s
switching
ripple and high frequency noise with the adequate
phase lag at ωC.
The compensated loop gain will be as given in Figure 4:
T
ωZ1
ωo
Loop gain T(s)
ωZ2
-20dB/dec
Gd
ωc
0dB
ωp1
ω p2
T(s) = GPWM ⋅ GCOMP(s) ⋅ GVD(s)
=
1
VM
⋅ ωI ⋅ VI
s
1+ s
⋅
1+
ωZ1
s
ωP1
1+ s
⋅
⋅
1
+
ωZ2
s
ωP2
1+
s
1
⋅
1
+
s
RC
L1
R
+
⋅ C4
s2L1C4
Power stage GVD(s)
-40dB/dec
ω ESR
Figure 4. Asymptotic diagrams of power stage and its
loop gain
Where:
GPWM = PWM gain and
VM = 1.5V, ramp peak to valley voltage of SC4602A/B.
2006 Semtech Corp.
13
www.semtech.com
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