WM8510GEDS/V データシートの表示（PDF） - Wolfson Microelectronics plc

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WM8510GEDS/V

Mono CODEC with Speaker Driver

Wolfson Microelectronics plc 

Pre-Production

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

tMCLKL

tMCLKH

tMCLKY

WM8510

Figure 1 System Clock Timing Requirements

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode

PARAMETER

System Clock Timing Information

MCLK System clock cycle time

MCLK duty cycle

SYMBOL

TMCLKY

TMCLKDS

MIN

TYP

Tbd

60:40

MAX

40:60

UNIT

ns

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

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PD Rev 4.1 December 2006

9

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