Z86M17 データシートの表示（PDF） - Zilog

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Z86M17

PCMCIA Interface Solution

Zilog 

Z86017/Z16017 PCMCIA Interface Solution

Product Specification

5

PCMCIA Bus

PC_DATA 15:0

PC_HA 10:0

PCMCIA

Host

PC_RDY//BSY/IREQ/HINT

PC_WAIT/IOCHRDY

PC_HCE1/HCS0

PC_HCE2/HCS1

PC_ATA/HOE

PC_HIOR

PC_HIOW

PC_HWE

PC_REG/DACK

PC_HRESET/HRESET

PC_BVD1/STSCHG/PDIAG

PC_WP/IOIS16/IOCS16

PC_BVD2/SPKR/DASP/DREQ

PC_INPACK/DREQ

Z86017

Attribute

Memory

Window 1

Start/Range

Decoder

Window 2

Start/Range

Decoder

Window 3

Start/Range

Decoder

ATA/IDE

Window

Decoder

EEPROM or µP

Control

Local Peripheral Bus

ATA_DATA 15:0

ATA_HCS0

ATA_HCS1

Chip Selects

ATA_HA0

ATA_HA1

ATA_HA2

Address Selects

ATA_HIOR

ATA_HIOW

I/O R/W

Strobes

ATA_MRD

ATA_MWR

Memory R/W

Strobes

ATA_IOCHRDY

ATA_IREQ

ATA_IOCS16

ATA_RESET

ATA_DREQ/BVD1

ATA_PDASP/EXTP_WP

ATA_PDIAG/ATA_BHE/RING_IN

ATA_DACK/BVD2

EXTP_PWDN

EXTP_AUDIO

EXTP_STSCHG/RES2

CLK

General

Peripheral

Bus Interface

PC_MCLK_IN

POR

EE_CS

EE_SK

EE_DI

EE_MASTER

EE_DO

M_PINT

POR

0.1 µF

CS CK DO DI

EEPROM

GND ORG NC VCC

Figure 2. Serial Port Master Mode Control

Serial Port Operation (SLAVE) Mode

When the ZX6017 is placed in serial port SLAVE mode (EE_Master

signal grounded on POR), the EEPROM sequencer is disabled and the

user must provide external hardware (microprocessor) with serial

interface to program CCRs and attribute memory. Additionally, if the

PCMCIA Interface Overview

PS012002-1201

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