49LF002 データシートの表示（PDF） - Silicon Storage Technology
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49LF002 Datasheet PDF : 36 Pages
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2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
Advance Information
TABLE 2: FWH WRITE CYCLE
Clock
Cycle
1
Field
Name
START
Field Contents
FWH[3:0]1
1110
FWH[3:0]
Direction
IN
2
IDSEL
0000 to 1111
IN
3-9
IMADDR
YYYY
IN
10
IMSIZE
0000 (1 byte)
IN
11
DATA
YYYY
IN
12
DATA
YYYY
IN
13
TAR0
1111
IN then Float
14
TAR1
1111 (float)
Float then OUT
15
RSYNC
0000
OUT
16
TAR0
1111
OUT then Float
17
TAR1
1111 (float)
Float then IN
1. Field contents are valid on the rising edge of the present clock cycle.
Comments
FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning
high) should be recognized. The START field contents
indicate a FWH memory read cycle.
Indicates which SST49LF00xA device should
respond. If the IDSEL (ID select) field matches the
value ID[3:0], then that particular device will respond
to the whole bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
This size field indicates how many bytes will be
transferred during multi-byte operations. The FWH
only supports single-byte writes. IMSIZE=0000b
This field is the least-significant nibble of the data byte.
This data is either the data to be programmed into the
flash memory or any valid flash command.
This field is the most-significant nibble of the data byte.
In this clock cycle, the master (Intel ICH) has driven the
then float bus to all ‘1’s and then floats the bus prior to
the next clock cycle. This is the first part of the bus
“turnaround cycle.”
The SST49LF00xA takes control of the bus during this
cycle. During the next clock cycle it will be driving the
“sync” data.
The SST49LF00xA outputs the values 0000, indicat-
ing that it has received data or a flash command.
In this clock cycle, the SST49LF00xA has driven the
bus to all then float ‘1’s and then floats the bus prior to
the next clock cycle. This is the first part of the bus
“turnaround cycle.”
The master (Intel ICH) resumes control of the bus during
this cycle.
T2.4 504
CLK
FWH4
FWH[3:0]
STR IDS
FIGURE 2: WRITE WAVEFORMS
IMADDR
IMS
DATA
TAR RSYNC
TAR
504 ILL F60.1
©2001 Silicon Storage Technology, Inc.
4
S71161-06-000 9/01 504
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