8600V データシートの表示（PDF） - Lattice Semiconductor

部品番号

コンポーネント説明

メーカー

8600V

3.3V In-System Programmable SuperBIG™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 8600V

Output Control Organization

In addition to the data input and output to the I/O cells,

each I/O cell can have up to six different I/O cell control

signals. In addition to the internal OE control, the five

control signals for each I/O cell consist of pin OE control,

clock enable, clock input, asynchronous preset and asyn-

chronous reset. All of the I/O control signals can be driven

either from the dedicated external input pins or from the

internal control bus.

The output enable of each I/O cell can be driven by 21

different sources – 16 from the output control bus, four

from the Global OE pins and one from the Test OE pin.

The Global OE signals and Test OE signal are driven

from the dedicated external control input pins.

The 16-bit wide output control buses are organized in four

different quadrants as shown in Figure 5. Since each

GLB is capable of generating the output control signals,

each of the output control bus signals can be driven from

a unique GLB. The 30 GLBs can generate a total of 30

unique I/O control signals. Referring to Figure 2, the GLB

generates its output control signal from control product

term (PT81).

Figure 5 also illustrates how the quadrant clocks are

routed to the appropriate quadrant I/O cells.

Figure 5. Output Control Bus and Quadrant Organization

Quadrant 0, 16-Bit Wide Output Control Bus

(I/O B0-B4 <0-11>, QIOCLK0)

GLB

Generated

Output

Control

(see Figure 2)

From PT81

Quadrant 2, 16-Bit Wide Output Control Bus

(I/O B0-B4 <12-23>, QIOCLK2)

8

OE Bus/8600V.eps

Share Link: