AN221D04-DEVLP データシートの表示（PDF） - Unspecified

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AN221D04-DEVLP

Dynamically Reconfigurable FPAA With Enhanced I/O

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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O

PRODUCT AND ARCHITECTURE OVERVIEW

The AN221E04 device consists of a 2x2 matrix of fully

Configurable Analog Blocks (CABs), surrounded by a fabric of

programmable interconnect resources. Configuration data is

stored in an on-chip SRAM configuration memory. Compared

with the first-generation FPAAs, the Anadigmvortex architecture

provides a significantly improved signal-to-noise ratio as well as

higher bandwidth. These devices also accommodate nonlinear

functions such as sensor response linearization and arbitrary

waveform synthesis.

The AN221E04 device features an advanced input/output

structure that allows the FPAA to be programmed with up to six

outputs – or triple the number provided by the ANx20E04

devices. The AN221E04 devices have four configurable I/O cells

and two dedicated output cells. For I/O-intensive applications, this

means a single FPAA can now be used to process multiple

channels of analog signals where two or more such devices were

previously needed.

In addition, the AN221E04 devices allow designers to implement

an integrated 8-bit analog-to-digital converter on the FPAA,

eliminating the potential need for an external converter. Using this

new device, designers can route the digital output of the A/D

converter off-chip using one of the dedicated output cells.

Figure 1: Architectural overview of the AN221E04 device

With dynamic reconfigurability, the functionality of the

AN221E04 can be reconfigured in-system by the designer or

on-the-fly by a microprocessor. A single AN221E04 can thus

be programmed to implement multiple analog functions

and/or to adapt on-the-fly to maintain precision operation

despite system degradation and aging.

PRODUCT FEATURES

• Dynamic reconfiguration

• Four configurable I/O cells, two dedicated output cells

• 8-bit SAR analog–to–digital converter

• Fully differential architecture

• Fully differential I/O buffering with options for single ended

to differential conversion

• Low input offset through chopper stabilized amplifiers

• 256 Byte Look-Up Table (LUT) for linearization and

arbitrary signal generation

• 4:1 Input multiplexer

• Typical Signal Bandwidth: DC-2MHz (Bandwidth is CAM

dependent)

• Signal to Noise Ratio:

o Broadband 80dB

o Narrowband (audio) 100dB

• Total Harmonic Distortion (THD): 80dB

• DC offset <100µV

• Package: 44-pin QFP (10x10x2mm)

o Lead pitch 0.8mm

• Supply voltage: 5V

ORDERING CODES

AN221E04-QFPSP

AN221E04-QFPTY

AN221E04-QFPTR

AN221D04-EVAL

AN221D04-DEVLP

Dynamically reconfigurable FPAA

Sample Pack

Dynamically reconfigurable FPAA

Tray (96 pcs)

Dynamically reconfigurable FPAA

Tape & Reel (1000 pcs)

AN221E04 Evaluation Kit

AN221E04 Development Kit

APPLICATIONS

• Real-time software control of analog system peripherals

• Intelligent sensors

• Adaptive filtering and control

• Adaptive DSP front-end

• Adaptive industrial control and automation

• Self-calibrating systems

• Compensation for aging of system components

• Dynamic recalibration of remote systems

• Ultra-low frequency signal conditioning

• Custom analog signal processing

[For more detailed information on the features of the AN221E04 device,

please refer to the AN121E04/AN221E04 User Manual]

DS030100-U006a - 3 -

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