HYB39S16160CT-7 データシートの表示（PDF） - Siemens AG

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HYB39S16160CT-7

16Mbit Synchronous DRAM

Siemens AG 

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

AC Characteristics (cont’d) 8, 9

TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns

Parameter

Symbol

Limit Values

Unit Note

-8

-10

min. max. min. max.

Common Parameters

Row to Column Delay time

tRCD

24 –

30 –

ns

Row Active time

tRAS

36 120k 45 120k ns

Precharge time

tRP

24 –

30 –

ns

Row Cycle time

tRC

60 120k 75 120k ns

Bank to Bank delay time

tRRD

16 –

20 –

ns

CAS to CAS delay time (same bank)

tCCD

1

–

1

–

CLK

Refresh Cycle

Self Refresh Exit time

Refresh period (4096 cycles)

tSREX

tREF

–

2 CLK + tRC

64 –

64

ns 13

ms 12

Read Cycle

Data Out Hold time

tOH

Data Out to Low Impedance time

tLZ

Data Out to High Impedance time

tHZ

CAS Latency = 3

CAS Latency = 2

CAS Latency = 1

3

–

3

–

ns

0

–

0

–

ns

14

–

5

–

6

ns

–

7

–

8

ns

–

19 –

25 ns

DQM Data Out Disable Latency

tDQZ

2

–

2

–

CLK

Write Cycle

Last Data-Input to Precharge

(Write Recovery Latency)

CL = 1, 2 tDPL

1

–

1

–

CLK

CL = 3

2

–

2

–

CLK

DQM Write Mask Latency

tDQW

0

–

0

–

CLK

Semiconductor Group

17

1998-10-01

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