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HYB39S16400AT-10 データシートの表示(PDF) - Siemens AG

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HYB39S16400AT-10
Siemens
Siemens AG Siemens
HYB39S16400AT-10 Datasheet PDF : 22 Pages
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HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Clock Frequency and Latency
Parameter
Clock frequency
Clock Cycle time
CAS latency
Row to Column delay
RAS latency
Row Active time
Row Precharge time
Row Cycle time
Last Data-In to Precharge (Write Recovery)
Last Data-In to Active/Refresh
Bank to Bank delay time
CAS to CAS delay time
Write latency
DQM Write Mask latency
DQM Data Disable latency
Clock Suspend latency
Symbol
Speed Sort
-8
-10
max. tCK
125 83 100 66
min. tCK
8 12 10 15
min. tAA
3232
min. tRCD
3232
min. tRL
6464
min. tRAS
5353
max. tRAS
120 120 120 120
min. tRP
3232
min. tRC
8585
min. tDPL
2121
min. tDPL + tRP 5
3
5
3
min. tRRD
2 22 2
min. tCCD
1111
fixed tWL
0000
fixed tDQW
0000
fixed tDQZ
2222
fixed tCSL
1111
Unit
MHz
ns
CLK
CLK
CLK
CLK
µs
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Semiconductor Group
20
1998-10-01

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