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CY7C1486V33(2004) データシートの表示(PDF) - Cypress Semiconductor

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CY7C1486V33
(Rev.:2004)
Cypress
Cypress Semiconductor Cypress
CY7C1486V33 Datasheet PDF : 30 Pages
First Prev 21 22 23 24 25 26 27 28 29 30
PRELIMINARY
CY7C1480V33
CY7C1482V33
CY7C1486V33
Document History Page
Document Title: CY7C1480V33/CY7C1482V33/CY7C1486V3372-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Document Number: 38-05283
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
114670 08/06/02
PKS New Data Sheet
*A
118281 01/21/03
HGK Changed tCO from 2.4 to 2.6 ns for 250 MHz
Updated features on page 1 for package offering
Removed 30-MHz offering
Updated Ordering Information
Changed Advanced Information to Preliminary
*B
233368 See ECN NJY Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 250-MHz speed grade offering and included 225-MHz speed bin
Changed package outline for 165FBGA package and 209-ball BGA package
Removed 119-BGA package offering
*C
299452 See ECN SYT Removed 225-MHz offering and included 250-MHz speed bin
Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin
Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100
TQFP Package on Page # 20
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages.
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
Document #: 38-05283 Rev. *C
Page 30 of 30

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