CY7C1482V33-200BZXC データシートの表示（PDF） - Cypress Semiconductor

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CY7C1482V33-200BZXC

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Cypress Semiconductor 

CY7C1480V33

CY7C1482V33

CY7C1486V33

.Document History Page

Document Title: CY7C1480V33/CY7C1482V33/CY7C1486V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Document Number: 38-05283

REV.

Orig. of

ECN NO. Issue Date Change

Description of Change

**

114670 08/06/02

PKS New Data Sheet

*A

118281 01/21/03

HGK Changed tCO from 2.4 to 2.6 ns for 250 MHz

Updated features on page 1 for package offering

Removed 30-MHz offering

Updated Ordering Information

Changed Advanced Information to Preliminary

*B

233368 See ECN NJY Changed timing diagrams

Changed logic block diagrams

Modified Functional Description

Modified “Functional Overview” section

Added boundary scan order for all packages

Included thermal numbers and capacitance values for all packages

Included IDD and ISB values

Removed 250-MHz speed grade offering and included 225-MHz speed bin

Changed package outline for 165FBGA package and 209-ball BGA package

Removed 119-BGA package offering

*C

299452 See ECN SYT Removed 225-MHz offering and included 250-MHz speed bin

Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin

Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100

TQFP Package on Page # 20

Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA

Packages

Added comment of ‘Lead-free BG packages availability’ below the Ordering

Information

*D

323080 See ECN

PCI Unshaded 200 and 167 MHz speed bin in the AC/DC Table and Selection

Guide

Address expansion pins/balls in the pinouts for all packages are modified as

per JEDEC standard

Added Address Expansion pins in the Pin Definitions Table

Added Truth Table and Note# 7 for CY7C1486V33 on page# 11

Added Industrial Operating Range

Modified VOL, VOH test conditions

Removed comment of ‘Lead-free BG packages availability’ below the

Ordering Information

Updated Ordering Information Table

*E

416193 See ECN NXR Converted Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Changed the description of IX from Input Load Current to Input Leakage

Current on page# 19

Changed the IX current values of MODE on page # 19 from -5 µA and 30 µA

to -30 µA and 5 µA

Changed the IX current values of ZZ on page # 19 from -30 µA and 5 µA

to -5 µA and 30 µA

Changed VIH < VDD to VIH < VDD on page # 19

Replaced Package Name column with Package Diagram in the Ordering

Information table

Updated the Ordering Information Table

*F

470723 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

Changed tTH,tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

Switching Characteristics table

Updated the Ordering Information table

*G

486690 See ECN VKN Corrected the typo in the 209-Ball FBGA pinout.

(Corrected the ball name H9 to VSS from VSSQ).

Document #: 38-05283 Rev. *G

Page 31 of 31

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