FM3104-S データシートの表示（PDF） - Unspecified
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FM3104-S Datasheet PDF : 22 Pages
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FM3104/16/64/256
01h
/OSCEN
Reserved
CALS
CAL.4-0
CAL/Control
D7
D6
D5
D4
D3
D2
D1
D0
OSCEN
Reserved
CALS
CAL.4
CAL.3
CAL.2
CAL.1
CAL.0
/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the
oscillator can save battery power during storage. On a power-up without battery, this bit is set to 1. Battery-
backed, read/write.
Reserved bits. Do not use. Should remain set to 0.
Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction from
the time-base. Calibration is explained on page 7. Nonvolatile, read/write.
These five bits control the calibration of the clock. Nonvolatile, read/write.
00h
Flags/Control
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
CF
Reserved
Reserved
Reserved
CAL
W
R
CF
CAL
W
R
Reserved
Century Overflow Flag. This bit is set to a 1 when the values in the years register overflows from 99 to 00. This
indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record the new
century information as needed. This bit is cleared to 0 when the Flag register is read. It is read-only for the user.
Battery-backed, read/write.
Calibration Mode. When set to 1, the clock enters calibration mode. When CAL is set to 0, the clock operates
normally, and the CAL/PFO pin is controlled by the power fail comparator. Read/write.
Write Time. Setting the W bit to 1 freezes updates of the user timekeeping registers. The user can then write
them with updated values. Setting the W bit to 0 causes the contents of the time registers to be transferred to the
timekeeping counters. Read/write.
Read Time. Setting the R bit to 1 copies a static image of the timekeeping core and place it into the user
registers. The user can then read them without concerns over changing values causing system errors. The R bit
going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again.
Read/write.
Reserved bits. Do not use. Should remain set to 0.
Two-wire Interface
The FM31xxx employs an industry standard two-
wire bus that is familiar to many users. This product
is unique since it incorporates two logical devices in
one chip. Each logical device can be accessed
individually. Although monolithic, it appears to the
system software to be two separate products. One is
a memory device. It has a Slave Address (Slave ID =
1010b) that operates the same as a stand-alone
memory device. The second device is a real-time
clock and processor companion which have a unique
Slave Address (Slave ID = 1101b).
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is
controlling the bus is the master. The master is
responsible for generating the clock signal for all
operations. Any device on the bus that is being
controlled is a slave. The FM31xxx is always a slave
device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. The figure
below illustrates the signal conditions that specify
the four states. Detailed timing diagrams are shown
in the Electrical Specifications section.
SCL
SDA
7
6
0
Stop
Start
Data bits
Data bit Acknowledge
(Master) (Master)
(Transmitter)
(Transmitter) (Receiver)
Figure 8. Data Transfer Protocol
Rev 0.2
May 2003
Page 13 of 22
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