KS8695P データシートの表示（PDF） - Micrel

部品番号

コンポーネント説明

メーカー

KS8695P

Integrated Multi-Port PCI Gateway Solution

Micrel 

Micrel, Inc.

KS8695P

Switch Engine

• 5-Port 10/100 integrated switch with one WAN and four LAN physical layer transceivers

• 16Kx32 on-chip SRAM for frame buffering

• 1.4Gbps on-chip memory bandwidth for wire-speed frame switching

• 10Mbps and 100Mbps modes of operation for both full and half duplex

• Supports 802.1Q tag-based VLAN and port-based VLAN

• Supports 8.2,1p-based priority, DiffServ priority, and post-based priority

• Integrated address look-up engine, supports 1K absolute MAC addresses

• Automatic address learning, address aging, and address migration

• Broadcast storm protection

• Full-duplex IEEE 802.3x flow control

• Half-duplex back pressure flow control

• Supports IGMP snooping

• Spanning Tree Protocol support

Advanced Memory Controller Features

• Supports glueless connection to two banks of ROM/SRAM/FLASH memory with programmable 8/16/32 bit data bus and

programmable access timing

• Supports glueless connection to two SDRAM banks with programmable 8/16/32-bit data bus and programmable

RAS/CAS latency

• Supports three external I/O banks with programmable 8/16/32-bit data bus and programmable access timing

• Programmable system clock speed for power management

• Automatic address line mapping for 8/16/32-bit accesses on Flash, ROM, SRAM, and SDRAM interfaces

Direct Memory Access (DMA) Engines

• Independent MAC DMA engine with programmable burst mode for WAN port

• Independent MAC DMA engine with programmable burst mode for LAN ports

• Supports little-endian byte ordering for memory buffers and descriptors

• Contains large independent receive and transmit FIFOs (3KB receive/3KB transmit) for back-to-back packet receive,

and guaranteed no under-run packet transmit

• Data alignment logic and scatter gather capability

Protocol Engine and XceleRouter™ Technology

• Supports IPv4 IP header/TCP/UDP packet checksum generation for host CPU offloading

• Supports IPv4 packet filtering based on checksum errors

Network Interface

• Features five MAC units and five PHY units

• Supports 10BASE-T and 100BASE-TX on all LAN ports and one WAN port. Also supports 100BASE-FX on the WAN

port and on one LAN port

• Supports automatic CRC generation and checking

• Supports automatic error packet discard

• Supports IEEE 802.3 auto-negotiation algorithm of full-duplex and half-duplex operation for 10Mbps and 100Mbps

• Supports full-/half-duplex operation on PHY interfaces

• Fully compliant with IEEE 802.3 Ethernet standards

• IEEE 802.3 full-duplex flow control and half-duplex backpressure collision flow control

• Supports MDI/MDI-X auto-crossover

May 2006

16

M9999-051806

Share Link: