M69AW024B
Figure 13. W Controlled, Continuous Write AC Waveforms
A0-A19
ADDRESS VALID
tGHAX
ADDRESS VALID
tAVWL
tWLAX
tWLWL
ADDRESS VALID
tAVWL
E1
tGHEL
W
tELWL
tWLWH
tWHWL
UB, LB
tGHBH
tBLWL
tWHBH
tBLWL
G
DQ0-DQ15
tGHWL
tGHQZ
tDVWH
VALID DATA INPUT
tWHDX
AI07413C
Note: 1. E2 must be High during the Write cycle.
Figure 14. E1 Controlled, Read/Write AC Waveforms
A0-A19
ADDRESS VALID
tEHAX
ADDRESS VALID
tAVEL
tELAX
tELEL
tAVEL
ADDRESS VALID
E1
tEHEL1
tELEH1
tEHEL1
tEHWH
tWHEL
tEHWL
tWLEL
ELGL
W
UB, LB
tEHBH
tBLEL
tEHBH
tBLGL
G
DQ0-DQ15
tEHQZ
tEHQX
READ DATA OUTPUT
tGHEL
tDVEH
tEHDX
WRITE DATA INPUT
tGLQX
Note: 1. Write address is valid from the falling edge of either E1 or W, whichever occurs later.
AI07414C
20/29