I.MX27L データシートの表示（PDF） - Freescale Semiconductor

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I.MX27L

Multimedia Applications Processor

Freescale Semiconductor 

Signal Descriptions

– Support 16 reference frame for H.264 decoding

– Quarter-pel and half-pel accuracy motion estimation

– [+/-16, +/-16] Search range

– Unrestricted motion vector

— All variable block sizes are supported (in case of encoding, 8 × 4, 4 × 8, and 4 × 4 block sizes

are not supported).

— MPEG-4 AC/DC prediction and H.264 Intra prediction

— H.263 Annex I, J, K(RS = 0 and ASO =0), and T are supported. In case of encoding, the Annex

I and K(RS=1 or ASO=1) are not supported.

— CIR (Cyclic Intra Refresh)/AIR (Adaptive Intra Refresh)

— Error resilience tools

– MPEG-4 re-synchronize marker and data-partitioning with RVLC (fixed number of

bits/macroblocks between macroblocks)

– H.264/AVC FMO and ASO

– H.263 slice structured mode

— Bit-rate control (CBR and VBR)

• Pre/post rotation/mirroring

— 8 rotation/mirroring modes for image to be encoded

— 8 rotation/mirroring modes for image to be displayed

• Programmability

— Embeds 16-bit DSP processor that is dedicated to processing bitstream and driving codec

hardware

— General purpose registers and interrupt generation for communication between system and

video codec module

3 Signal Descriptions

This section discusses the following:

• Identifies and defines all device signals in text, tables, and (as appropriate) figures. Signals can be

organized by group, as applicable.

• Contains pin-assignment/contact-connection diagrams, if the sequence of information in the data

sheet requires them to be included here.

Table 3 shows the i.MX27/MX27L signal descriptions.

Table 3. i.MX27/MX27L Signal Descriptions

Pad Name

Function/Notes

A [13:0]

External Bus/Chip Select (EMI)

Address bus signals, shared with SDRAM/MDDR, WEIM and PCMCIA, A[10] for

SDRAM/MDDR is not the address but the pre-charge bank select signal.

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

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